Method and apparatus for conserving power on a...

Details Method and apparatus for conserving power on a... Method and apparatus for conserving power on a...

2005-07-26

2005-07-26

Cottingham, John R. (Department: 2116)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

Reexamination Certificate

active

06922783

ABSTRACT:
A multiple processor integrated circuit has a first processor-first level cache combination powered by a first power terminal, and a second processor-first level cache combination powered by a second power terminal. There is common circuitry coupled to each processor-cache combination. In a particular embodiment, the processor-cache combinations are capable of receiving independently controlled power over the power terminals.

REFERENCES:
patent: 5890217 (1999-03-01), Kabemoto et al.
patent: 6035358 (2000-03-01), Tanikawa
patent: 6108764 (2000-08-01), Baumgartner et al.
patent: 6141762 (2000-10-01), Nicol et al.
patent: 6598108 (2003-07-01), Ashida et al.
patent: 6711691 (2004-03-01), Howard et al.

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