Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – Small lead frame for connecting a large lead frame to a...
Reexamination Certificate
2002-04-22
2004-10-19
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
Small lead frame for connecting a large lead frame to a...
C257S676000, C257S686000, C257S692000, C257S724000, C257S784000, C257S787000, C438S109000, C438S123000, C438S124000, C438S127000, C029S827000, C029S841000, C029S855000, C361S813000
Reexamination Certificate
active
06806559
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electronic modules comprised of stacked integrated circuit carrying chips and more particularly to the method and apparatus for providing a connection among and with memory chips as an assembly of stacked memory chips.
2. Description of the Prior Art
High-density electronic packages, which are capable of incorporating more electronic capacity in a given space, or reducing the space required for a given amount of electronic capacity. Such packages are particularly useful as computer memories, control logic, arithmetic units, and the like wherein a plurality of similar chips can be advantageous combined into a single assembly or module.
The electronic density is obtained by means of a structure in which integrated circuit (IC) chips are stacked to form a three-dimensional structure. The stacked chip structure: (a) has at least one interconnect plane which is adapted to be electrically connected to external circuitry; and (b) contains within its volume a very extensive electronic system. The term “interconnect plane” signifies that electrical leads extend to that planar surface of the stacked chip structure.
In various prior applications and patents assigned to the assignee of this application, stacks of silicon IC chips have been proposed. One of those applications is U.S. Pat. No. 4,706,166. That patent discloses a three-dimensional module of stacked layers, or chips, each of which layers carries IC circuits whose leads extend to a common interconnect plane of the module. Electrically conductive bumps deposited on the access plane of the module are aligned with, and bonded to, electrically conductive bumps on a supporting substrate, thereby connecting the circuitry in the stacked layers to external circuitry.
Various limitations and deficiencies in the prior developments have led to the present invention. One such limitation is the fact that IC chips, such as memory devices, which are preferably obtained as standard (off-the-shelf) items from suppliers, must be modified to provide external leads only at one edge, instead of two edges, of each chip.
Perhaps the most critical problems encountered have been due to the electrically conductive properties of the material of the stacked chips, except for such materials as gallium arsenide and sapphire. Because the electrical leads at the interconnect plane must be insulated from the semiconductor material, it has been necessary to apply passivation material on the interconnect plane, and then to form T-shaped electrical connections by applying thin-film metallization to the interconnect plane.
These “T-connects” are fragile and therefore not very reliable. In the case of a silicon stack, the reliability of the “T-connects” depends to a large extent on the quality of the passivation layer. Another problem centers around the epoxy glue between layers, which is troublesome in several ways. Glue thickness variations, for example, can cause problems during certain processing steps, and the glue limits the stack's operating temperature to about 10° C. It also limits the choice of material for the bonding bumps (to avoid degrading the glue and passivation due to high temperature). In addition to the “T-connect” problem and the glue problem, there is also a problem with flip-chip bonding (bump bonding) of the stacked chip module to a substrate. Flip-chip bonding has been less reliable as a method for making electrical interconnections than other methods, such as TAB bonding and wire bonding. In particular, it is not very practical in a mass production environment.
Another issue addressed by the present invention concerns heat transfer, particularly where the IC chips have high power requirements. Although silicon has reasonable heat-conducting properties, there is still the possibility of overheating problems in silicon stacks. Furthermore, the heat dissipation problem appears almost insurmountable (in stacked chip modules), if non-heat-conducting chips made of poor thermally-conducting material, such as gallium arsenide (GaAs), are used.
Such chips have certain advantages over silicon, including their ability to provide much higher speed electronic signals. However, the use of GaAs devices at higher speeds and temperatures, in the future can be expected to create packaging problems. As operating frequency increases into the gigahertz range, chip temperature increases and electrical/material properties begin to vary significantly. As a result, many other electrical properties are also affected; they include signal propagation delay, signal rise time, and characteristic impedances. Requirements for innovative denser packaging to help alleviate these problems have become critical. It is therefore obvious that special temperature considerations must be given to the packaging of GaAs devices to avoid degradation of their high speed performance.
To satisfy these needs the prior art has provided a frame carrier in which the chip is embedded as shown in U.S. Pat. No. 4,764,846. While effective to meet the foregoing problems, this approach entails processing and manufacturing steps which add significantly to the cost of the assembled stack of chips.
Therefore, what is needed is an inexpensive and easily fabricated method and apparatus by which similar prefabricated, packaged chips may be stacked together and connected both to each other and to the external world.
BRIEF SUMMARY OF THE INVENTION
The invention is an apparatus comprising a plurality of prepackaged integrated circuits, each with a first plurality of exterior leads connected to a second plurality of interior wires, having at least one exterior lead which is not connected to any interior wire. The plurality of prepackaged integrated circuits are vertically stacked on each other so that like leads are aligned with each. The prepackaged integrated circuits are modified so that the first plurality of exterior leads are removed exposing ends of the second plurality of interior wires on a collective lateral surface of the vertically stacked prepackaged integrated circuits. A plurality of metallizations are disposed on the collective lateral surface connecting selected ones of the second plurality of interior wires together and separately connected to selected other ones of second plurality of interior wires.
The apparatus further comprises a contact layer having contact pads defined therein. The contact layer is disposed on the vertically stacked prepackaged integrated circuits. The plurality of metallizations are coupled to the contact pads. The plurality of metallizations are coupled to the contact pads via leads disposed in the contact layer and extending to the collective lateral surface. The contact layer has an exposed top surface and the contact pads are defined on the exposed top surface.
5. The apparatus of claim
2
wherein the contact layer has an exposed top surface and wherein the contact pads are defined on the exposed top surface.
The prepackaged integrated circuits have a plurality of types of circuit terminals. A first group of metallizations, which connect selected ones of the second plurality of interior or bonding wires together, are disposed vertically on the collective lateral surface and are connected to a selected one of the types of circuit terminals of each of the plurality of prepackaged integrated circuits to form a common connection among the selected type of circuit terminal. A second group of metallizations, which are separately connected to a selected one of second plurality of interior or bonding wires, correspond to a selected type of circuit terminal for each of the plurality of prepackaged integrated circuits. This second group of metallizations are disposed in part vertically on the collective lateral surface and are laterally offset one from the other to allow separate access to each one of the plurality of prepackaged integrated circuits through the selected type of circuit terminal.
This second group of offset metallizations are disposed in an NC or “no connection” region
Albert Douglas M.
Gann Keith D.
Andras Joseph E.
Chambliss Alonzo
Irvine Sensors Corporation
Myers Dawes Andras & Sherman LLP
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