Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-06-30
2004-05-11
Lefkowitz, Sumati (Department: 2833)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S310000
Reexamination Certificate
active
06735657
ABSTRACT:
The present invention relates to connecting two or more serial interfaces and in particular a two-wire TX/RX interface, as commonly found on a computer CPU, to a one-wire interface so as to provide high data transmission speeds.
BACKGROUND INFORMATION
Many electronic devices or components include one or more interfaces for transmitting and/or receiving data in a serial fashion. One example is a computer central processing unit (CPU) which typically includes a two-wire serial interface, providing a first wire or pin for data transmit and a second wire or pin for data receive purposes.
The two-wire or two-pin serial interface is by no means a universal configuration. It is not uncommon to use electronic devices or components having one or more serial interfaces which provide only a single wire or pin for data. Those of skill in the art will understand that, while a device or component may provide a single wire or pin for serial transmission of data in both directions (both transmit and receive) or can have a two-wire serial interface configuration (providing a first wire or pin for transmit of serial data and a second wire or pin for receipt of serial data) the interface, component or device may have numerous other wires or pins including, e.g., power, ground, control pins or wires and the like. While an electronic device or component may have a particular type of serial interface, such as a one-wire serial interface or two-wire serial interface, it is not uncommon for devices or components to also have other interfaces such as numerous serial interfaces, one or more parallel interfaces, wireless links and the like.
One example of a one-wire serial interface is the interface provided in at least some audio processing circuits such as that sold under the trade name Quad Subscriber Line Audio Processing Circuit (QSLAC) available from Advanced Micro Devices (AMD).
In some circumstances, it is desired to provide for both read and write serial communication between the two wire serial interface and a single wire serial interface. As will be understood by those of skill in the art, read and write operations at the two interfaces are complementary in the sense that an operation which represents a write operation at the two-wire interface, is a read operation at the one-wire interface and vice versa. One possible approach is to connect the wires or pins of the two wire interface, pulled up to a desired voltage (such as Vcc) with a resistor. It has been found, however, that this configuration can lead to relatively low limits on the speed of data transmission, especially when the single wire is used for both transmit and receive directions.
Accordingly, it would be useful to provide a system, method and apparatus for providing communication between a two wire serial interface and a single wire interface at relatively high data transmission speeds. Preferably, such a system, method and apparatus can be implemented at relatively low cost, such as by using at least some components which are already present in the system (e.g., for another purpose).
SUMMARY OF THE INVENTION
The present invention includes a recognition of the existence, nature and/or source of problems in previous approaches, including as described herein.
In one aspect, the present invention provides a connection between a two-wire serial interface and a one-wire serial interface which substantially avoids more than one current source being active or connected at any given time. In one embodiment, a control device, which may be a CPU, under the control of microprogramming or other software, controls the interfaces so as to avoid both write sources (or current sources) being active and/or connected at the same time.
In one embodiment, each wire or pin of a two-wire serial interface is provided to a controllable buffer, controlled by a control signal. The CPU or other control device assures that the write buffer is off or inactive during any time that the one-wire serial interface is able to transmit or write.
In one embodiment, the single-wire interface is configured such that transmit or write operations cannot be performed until a write-enable (or similar signal) is received, e.g., from a CPU, i.e. the same control device which controls the buffers of the two-wire interface. Accordingly, the control device will preferably inhibit the write buffer of the two-wire serial interface whenever a write-enable is sent to, or effective at, the single-wire interface and similarly the control device will disable write capability at the single-wire interface whenever the write buffer of the two-wire interface is enabled.
By providing for selective enablement/disablement of write capabilities, the present invention can avoid the approach of using a “mixer”, such as a pull-up resistor on the common line. By eliminating the need for a pull-up resistor or similar device, it is possible to avoid unduly long rise-times or fall-times and, in this way, relatively high digital signal transmission rates can be provided.
In one aspect, a two-wire interface having a receive wire and a transmit wire is coupled for communication with a single-wire serial interface to provide for relatively high-speed data transmission. In one aspect, controllable buffers are coupled to the transmit and receive lines of the two-wire serial interface. The outputs from the two buffers are coupled to a common line which is also coupled to the single line of the single-wire interface. The transmit buffer and/or read buffer and/or transmission from the single-wire interface are controlled, e.g., such as using control signals provided by software, such that the transmit buffer from the two-wire interface is enabled only when transmission from the single-wire interface is disabled and transmission from the single-wire interface is permitted only when the transmit buffer of the two-wire interface is disabled. By this type of system, it is possible to avoid coupling which involves a pull-up transistor and the like, avoiding lengthening the rise time or fall time of signals and providing the potential for relatively high data transmission rates. In one aspect, the increase in data transmission speed is roughly proportional to the rise time and/or fall time (or combination thereof) of the signal. The rise time/fall time is generally proportional to the current source/sink ability of the drivers and inverse to the pull-up resistor value. A typical increase in transmission speed, according to an embodiment of the invention is one to two orders of magnitude, such as an increase from about 40 kilobits per second (kbps) to about 1 megabits per second (Mbps), prefer about 2 Mbps.
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AMD Product Brief; AM79Q02/021/031 (PCM only) and AM79Q06/061/062/063 (PCM/GCI) Quad Subscriber Line Audio-Processing Circuits: http://www.amd/com/products/cpd/prodover/wan/2004.html; pp. 1-3.
Falk Peter
Harrow Joseph C.
Huang Wen
Chung-Trans X.
Hickman Palermo & Truong & Becker LLP
Lefkowitz Sumati
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