Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-08-01
2003-07-08
Rinehart, Mark H. (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S314000, C711S201000
Reexamination Certificate
active
06591322
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to busses using a wired-AND protocol and, more particularly, to methods and apparatus for connecting devices in a bus system having multiple bus masters.
BACKGROUND OF THE INVENTION
The I
2
C bus system is an electronic bus for carrying commands and data between compatible devices connected to the bus. The system was developed and marketed by Philips Semiconductor Corporation and is described in detail in the I
2
C Specification, revision 2.0, Philips Semiconductor Corporation 1995, which specification is hereby incorporated by reference in its entirety. In the I
2
C bus system, two wires, called a serial data (SDA) line and serial clock (SCL) line, carry information between the devices connected to the bus. Both the SDA and SCL lines are bi-directional lines, connected to a positive supply voltage via pull-up resistors as shown in
FIG. 1
to form a “wired-AND” configuration. For example, in the bus configuration
100
illustrated in
FIG. 1
, the SDA line
108
and the SCL line
110
are connected to the V
DD
supply line
102
by pull-up resistors
104
and
106
, respectively. Other busses which use a similar protocol include the SMBus and Access. bus. Collectively, this type of bus system will be termed a “wired-AND” bus system. The remainder of the discussion will focus on the I
2
C bus system with the understanding that the discussion applies to these other bus systems as well.
When the bus
101
is free, both the SDA line
108
and the SCL line
110
are pulled to a “HIGH” state by the resistors
104
and
106
. The output stages of devices connected to the bus must have an open-drain or open-collector in order to form the wired-AND configuration. Two devices
112
and
114
are shown schematically in FIG.
1
. Device
112
has a clock output stage which includes output transistor
116
which is connected across the SCL line
110
and ground
118
. When a signal on the gate
117
of transistor
116
turns the transistor on, it pulls the SCL line
110
“LOW.” Clock signals on the SCL line
110
can be detected by means of buffer
120
whose output forms the “clock in” line
122
.
Similarly, device
112
has a data output stage which includes output transistor
124
which is connected across the SDA line
108
and ground
126
. When a signal on the gate
123
of transistor
124
turns the transistor on, it pulls the SDA line
108
“LOW.” Data signals on the SDA line
108
can be detected by means of buffer
128
whose output forms the “data in” line
130
. Device
114
also has a clock output transistor
132
and clock input buffer
134
and a data output transistor
136
and data input buffer
138
for communication with the SDA and SCL lines,
108
and
110
.
Devices on the bus communicate by periodically pulling the SDA and SCL lines
108
and
110
LOW-producing data and clock pulses on the lines
108
and
110
. In accordance with the I
2
C protocol, the data on the SDA line
108
must be stable when the clock line SCL
110
is HIGH. Thus, the HIGH or LOW state of the data line
108
can only change when the clock line
110
is LOW. Two unique situations arise, which situations are defined as START and STOP conditions. In particular, a HIGH to LOW transition on the SDA line
108
while the SCL line
110
is HIGH is defined as a START condition. A LOW to HIGH transition on the SDA line
108
while the SCL line
110
is HIGH is defined as a STOP condition.
Each device
112
,
114
on the bus
101
has a unique address and can operate as either a data transmitter or a data receiver, depending on the function of the device. For example, an LCD driver is always a data receiver, whereas a memory can both receive and transmit data. In addition to being transmitters and receivers, devices can also be bus masters or slaves when performing data transfers. A bus master is the device that initiates a data transfer on the bus, generates the clock signals required for that transfer and terminates that data transfer. During this transfer, any other device to which data is sent, or from which data is received, is considered a slave. The bus master may transmit data to a slave or receive data from a slave. In both cases, the clock signals are generated by the bus master. Bus master and slave relationships are not permanent and depend on which device initiated the data transfer at a given time.
More than one bus master device can be connected to bus
101
. Bus implementations with exactly one device capable of acting as a master are called single-master busses, while those with two or more devices capable of acting as bus masters are called multimaster busses. In a single-master bus system, the I
2
C protocol is very straightforward, with every transaction consisting of a START condition followed by one or more address and data phases, followed by a STOP condition. Thus, the START and STOP conditions frame all activity on the bus and hence define the duration during which the bus is busy.
In a single-master I
2
C bus, the only interesting error scenario that can present itself occurs when a slave device responds to an address or data phase with a negative-acknowledgement (NAK) response. A NAK response is represented as a HIGH signal level on the SDA line
108
during the acknowledge bit time, which is defined as the ninth clock pulse of any address or data phase. Since the I
2
C bus is a wired-AND configuration, a NAK response is equivalent to no response from a slave device. In the case of a NAK on an address phase, this may indicate that the slave device is busy and unable to accept I
2
C transactions at this time, that it is non-functional or simply missing.
Because NAK conditions happen only at well-defined points in a transaction, and because the interpretation of a NAK is straightforward, the response is not ambiguous. Most often, the bus master software may simply decide to retry a transaction that receives a NAK. The important observation is that NAK errors do not threaten the correct operation of the I
2
C bus itself; they affect only higher level protocol that is typically implemented in software.
Multimaster I
2
C bus implementations are dramatically more complex. The I
2
C protocol is essentially a carrier-sense multiple access with collision detection (CSMA/CD) scheme, which functions like an Ethernet system. However, unlike an Ethernet system, the I
2
C protocol lacks the higher layers of communication protocol that transform the Ethernet system into a reliable channel. As such, a large burden is placed on a multimaster I
2
C device. At every point in an I
2
C transmission, a bus master must be able to detect collisions with other bus masters and recover gracefully.
Some of these collision scenarios are particularly troublesome. For example, as described in the aforementioned I
2
C Specification, “arbitration” is the mechanism by which multiple bus master devices can drive the I
2
C bus simultaneously without causing data corruption. The basic arbitration mechanism relies on the open-collector nature of the bus; when two or more masters drive an address or data bit on the SDA line
108
, a LOW value driven by one or more bus masters will always win out over a HIGH value produced by other bus masters. Thus, any bus master attempting to drive a HIGH value during a bit time (by not driving the SDA line
108
LOW and allowing the pull-up resistor
104
to keep the line HIGH), but sensing a LOW value during the same bit time, will recognize that a collision has occurred with another master driving a LOW value and relinquish the bus. However, if multiple bus masters are driving the same sequences of bits, then no collision will be detected until the bit sequences differ. Thus, it is possible that a bus master will detect a collision between itself and another master at some arbitrarily late point in a transaction, or even not at all.
Loss of arbitration is the simplest error type to handle from a protocol perspective because it automatically forces the losing bus master off the bus, as defined in the aforementioned I
2
C specific
Ervin Joseph J.
Lach Jorge E.
Kudirka & Jobse LLP
Lee Christopher E.
Rinehart Mark H.
Sun Microsystems Inc.
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