Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-08-15
1999-12-07
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711120, 711153, 711154, G06F 1200, G06F 1300
Patent
active
060000139
ABSTRACT:
The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus. The controller circuits disposed in each of the cache memory devices compares the unique identification number with the predefined address bits, such that if the identification number and the predefined address bits match, the controller circuit provides control signals to enable its cache memory to execute the memory operation requested by the CPU at the cache memory location corresponding to the main memory address. In the event the identification does not match the predefined bits of the address, the memory controller circuit does not provide control signals to enable the memory to execute the memory operation and disables output driver circuits disposed within the cache.
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Banerjee Pradip
Ghia Atul V.
Lau Simon
Sony Corporation
Sony Electronics Inc.
Thai Tuan V.
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