Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1997-08-06
2000-05-30
Teska, Kevin J.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
716 7, 716 8, 716 12, G06F 1900, G06F 1750
Patent
active
060686626
ABSTRACT:
Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. The congestion reduction is achieved by first examining regions of the IC to determine whether horizontal or vertical congestion exists. If horizontal congestion exists, then the cells are moved, within the columns, vertically to give more room for the cells and in between the cells for the routing of the wires. If vertical congestion exists, then the cells are moved to different columns to alleviate congestion. The present invention discloses techniques of determining horizontal and vertical congestion and the techniques for moving the cells. The movement of the cells to other columns may create overlapping of the cells or overloading of the columns. The present invention also discloses the methods to resolve the overlapping and overloading problems.
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Andreev Alexander E.
Pavisic Ivan
Scepanovic Ranko
Choi Kyle J.
LSI Logig Corporation
Teska Kevin J.
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