Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2002-07-15
2004-06-01
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S008000, C710S022000, C710S053000, C710S104000, C710S105000, C710S100000, C710S305000
Reexamination Certificate
active
06745264
ABSTRACT:
BACKGROUND
Universal Serial Bus (USB) device interface controller logic usually consists of a transceiver interface, protocol engine, endpoint recognition logic, and special First In-First Out buffers (FIFOs) that handle some of the peculiar requirements of USB data transfer. In a processor-based device, one or more Direct Memory Access (DMA) engines are typically needed to move data into and out of the FIFOs.
In a typical design, these functions are discrete. The USB transceiver interface, protocol engine, and endpoint recognition logic may be available in one package. Alternatively, it may be implemented as three logical entities with the FIFOs and DMAs being separate components. Considerable effort may be required to select the proper pieces and interface them together.
Further, the endpoint recognition logic, FIFOs, and DMAs must be properly configured for each application. Configuration of the endpoint recognition logic is typically done either by hardcoding values into the logic itself, or by using scripts to modify code. The former approach is time-consuming and not very flexible. The latter approach typically results in code and logic that is difficult to understand and debug, and that is also rather inflexible. The FIFOs and DMA engines are typically configured and instantiated by hand, another time-consuming and error-prone process.
Another design methodology is to create hardware with some limited number of physical endpoints. These endpoints are then mapped to logical endpoints and controlled by software. This method provides even less flexibility in the design process and limited flexibility in using the designed hardware. This method suffers from the same issues of trying to interface separately designed components, or in designing new components from the ground up with matching interfaces.
Isochronous data transfers refer to processes where data is delivered with certain time constraints. For example, multimedia streams require an isochronous transport mechanism to ensure that data is delivered at the constant rate required for audio or video regeneration.
A single circular FIFO buffer
12
is shown in
FIG. 1. A
ring configuration using multiple buffers
14
is shown in FIG.
2
. The buffer configurations in
FIGS. 1 and 2
can each be used for processing isochronous data streams. In the singular circular FIFO
12
shown in
FIG. 1
, the isochronous data is placed in the buffer
12
starting at a beginning address. Once data reaches the end of the FIFO
12
, data starts over at the beginning address. Data can be read from the buffer
12
or written to the buffer
12
at any time.
In the case of the ring configuration of multiple buffers
14
shown in
FIG. 2
, the individual buffers
14
are sized according to the amount of data in the packets transporting the data either to or from the buffer. Once buffer
14
A is full (or empty), the data starts moving to or from buffer
14
B, and so on. Each individual buffer
14
A-
14
D is dedicated to only read or only write data until the buffer is either full or empty.
These two types of buffers have problems with an isochronous data flow. One problem with the buffers is the inefficiency in keeping track of the (micro)frame number associated with the isochronous data. Isochronous data transfers require that a time be associated with the appropriate data. Some mechanism must be in place to maintain that association.
In the case of the single circular FIFO
12
, the (micro)frame information would typically be embedded in the isochronous data, along with any header information. This scheme requires hardware to read the information out of the buffer, parse it to detect the header and frame information, and then extract the isochronous data.
The ring configuration of single buffers
14
also does not efficiently track frame numbers, as it would also typically embed the (micro)frame information in the isochronous data. Ring architectures can also accomplish the same task by instantiating registers associated with each buffer
14
A-
14
D to hold the (micro)frame information. But this requires additional hardware.
While the circular FIFO
12
is inefficient for isochronous transfers, it may be more efficient in handling other types of transfers, such as for Universal Serial Bus (USB) bulk, control, and interrupt transfers. In the case where a design requires an endpoint to transfer bulk data in one configuration and isochronous data in another configuration, different buffers are required for each configuration.
The present invention addresses this and other problems associated with the prior art.
SUMMARY OF THE INVENTION
Hardware Description Language (HDL) code is created for an interface controller so that logic requiring device-specific configuration refers to a parameter file. This set of parameters lets each of the components comprising the interface circuit provide support for a common configuration. Changing the hardware configuration of the entire interface controller system may be accomplished by simply modifying the one parameter file. These changes are then automatically reflected in all the components of the controller.
In another aspect of the invention, a control circuit divides a single memory into buffer partitions for each physical endpoint and identifies each endpoint as either isochronous or non-isochronous. A buffer partition is configured into a first FIFO mode for isochronous endpoints and configured into a second FIFO mode for non-isochronous endpoints.
REFERENCES:
patent: 6070208 (2000-05-01), Brief
patent: 6173355 (2001-01-01), Falik et al.
patent: 6266715 (2001-07-01), Loyer et al.
patent: 6408351 (2002-06-01), Hamdi et al.
patent: 6523081 (2003-02-01), Karlsson et al.
patent: 2002/0065966 (2002-05-01), Brief
patent: 2002/0078283 (2002-06-01), Pucell et al.
patent: 2003/0041205 (2003-02-01), Wu et al.
Luke David
Pew Frederick
Provencio Kris
Cypress Semiconductor Corp.
Gaffin Jeffrey
Marger & Johnson & McCollom, P.C.
Peyton Tammara
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