Method and apparatus for configurable multiple level cache with

Details Method and apparatus for configurable multiple level cache with Method and apparatus for configurable multiple level cache with

1997-08-06

2000-09-05

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711119, G06F 1200, G06F 1300

Patent

active

061157953

ABSTRACT:
A coherency controller for configurable caches. A base microprocessor design accommodates system configurations both with and without L2 cache tag and data arrays installed. Second level cache control logic exists within the microprocessor chip, and when the external second level cache tag and data arrays are removed their inputs to the microprocessor are tied to an inactive state. A configuration switch is set in the second level cache controller that causes snoop requests from a system bus to get reflected onto a first level cache snooping path. The first level cache status is then fed back to the second level cache controller, in a manner consistent with the timing required for support of a second level cache search, and fed into the second level cache status signal generation logic, effectively making the second level cache controller believe that the second level cache still exists for snooping. All other actions remain the same in the second level cache controller providing an effective and simple method for supporting snooping bus protocols. A result is that now every bus request snoops the first level cache without knowledge of presence of an L2 cache. This environment is provided to support entry level single processor configurations where the snooping requests only amount to input/output traffic.

REFERENCES:
patent: 5437042 (1995-07-01), Culley et al.
patent: 5737756 (1998-04-01), White et al.
patent: 5822765 (1998-10-01), Boatright et al.
patent: 5829035 (1998-10-01), James et al.

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