Method and apparatus for configurable address translation

Details Method and apparatus for configurable address translation Method and apparatus for configurable address translation

2010-01-28

2011-11-22

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000, C326S047000

Reexamination Certificate

active

08063660

ABSTRACT:
A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.

REFERENCES:
patent: 5276832 (1994-01-01), Holman, Jr.
patent: 6181163 (2001-01-01), Agrawal et al.
patent: 6903574 (2005-06-01), Chen et al.
patent: 7126372 (2006-10-01), Vadi et al.
patent: 2010/0036997 (2010-02-01), Brewer et al.

Affiliated with

Also associated with

Rating

Method and apparatus for configurable address translation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for configurable address translation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for configurable address translation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4276851