Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-09-05
2006-09-05
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S776000
Reexamination Certificate
active
07103822
ABSTRACT:
The present invention discloses CRC checking ‘N-bit at a time’ of data frames of lengths not necessarily in a multiple of the N-bit. While receiving the data frame, the data frame length is extracted from the protocol header and a misalignment is computed versus the ‘N-bit at a time’ value. Simultaneously, CRC is computed on each received N-bit of the data frame and an FCS register is updated. At each cycle, a checking is performed to know whether the data frame length has been extracted from the protocol header. While the data frame length is not yet known and more bits are left to process, the data frame is continued to be received and computed ‘N-bit at a time’. When the data frame length is known and no more bits are to be processed, the current value of the FCS register is compared to a pre-stored vector corresponding to the misalignment. If a match occurs, checking of the data frame passes and the data frame is accepted. If a match does not occur, checking of the data frame fails and the data frame may be rejected. Therefore, the present invention is capable of computing CRC of a data frame ‘N-bit at a time’ while the data frame length is not yet known.
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Glaise Rene
Verplanken Fabrice
Canale Anthony J.
Chaudry Mujtaba K.
De'cady Albert
Harding W. Riyon
International Business Machines - Corporation
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