Method and apparatus for computing test margins for at-speed...

Details Method and apparatus for computing test margins for at-speed... Method and apparatus for computing test margins for at-speed...

2011-01-18

2011-01-18

Doan, Nghia M (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C714S745000, C702S089000, C702S125000

Reexamination Certificate

active

07873925

ABSTRACT:
In one embodiment, the invention is a method and apparatus for computing margins for at-speed testing of integrated circuit chips. One embodiment of a method for computing a margin for at-speed testing of an integrated circuit chip design includes computing a statistical chip slack for the chip, computing a statistical test slack for the chip, and computing the margin from the chip slack and the test slack.

REFERENCES:
patent: 7539893 (2009-05-01), Ferguson
patent: 7620921 (2009-11-01), Foreman et al.
patent: 2008/0010032 (2008-01-01), Sugiyama
patent: 2009/0119629 (2009-05-01), Grise et al.

Affiliated with

Also associated with

Rating

Method and apparatus for computing test margins for at-speed... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for computing test margins for at-speed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for computing test margins for at-speed... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2682858