Method and apparatus for computing feature density of a chip...

Details Method and apparatus for computing feature density of a chip... Method and apparatus for computing feature density of a chip...

2008-01-22

2008-01-22

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07322018

ABSTRACT:
One embodiment of the present invention provides a system that computes feature density for a number of areas within a layout by moving a window across the layout, which allows the system to identify areas in the layout that violate a design rule. During operation, the system receives a layout. Next, the system places the window at a first location in the layout. The system then computes the feature density value based on the features within the window at the first location. Next, the system determines a second location in the layout based on the first location and the feature density value. The system then moves the window to the second location. Next, the system computes the feature density value based on the features within the window at the second location. Note that determining the second location in the layout based on the feature density value computed at the first location instead of using a constant displacement from the first location allows the system to accurately identify an area that violates the design rule.

REFERENCES:
patent: 6446239 (2002-09-01), Markosian et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 7093212 (2006-08-01), DeCamp et al.
patent: 7155689 (2006-12-01), Pierrat et al.

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