Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-03
2003-04-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S002000, C703S015000, C703S019000, C702S125000
Reexamination Certificate
active
06553550
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
REFERENCE TO A MICROFICHE INDEX
Not Applicable.
BACKGROUND OF THE INVENTION
This invention relates in general to timing analysis and verification of integrated circuit designs, and in particular to a computer method which enables said analysis to be performed using correlated relationships between the delays that normally occur in components of such circuits.
One of the most important steps in digital design is performing a timing analysis to determine if the circuit meets logic and performance requirements. The essence of such an analysis is determining whether a signal arrives at its destination within some time limit so that it may successfully interact with other signals and logic components. Many signals and time constraints (up to thousands or millions) exist in a modern digital logic chip. The traditional method of timing analysis, pencil and paper, quickly overwhelms a design engineer for a large circuit. Fortunately, the recent past has seen the emergence of computer programs which automate the construction of complex timing models. The designer enters timing and signal information graphically and the program automatically computes whether the circuit meets timing requirements or not. Design optimization can proceed relatively quickly since information does not have to be completely re-entered each time a change is conceived.
Several timing analysis software packages are available on the open market. U.S. Pat. No. 5,576,979 refers to one such product by Chronology™ Corp. Synapticad, Inc. manufactures another one called WaveFormer Pro™. In addition, related products, such as circuit simulators and static timing analyzers, exist which can do timing analysis. These products will be described in greater detail later, especially as they relate to delay correlation.
The critical data entered into a timing analysis includes the signals produced by logic components (or clocks), and the delays associated with these components and their interconnections. Also entered are any timing requirements such as the fact that a signal should arrive at a particular component a certain time before some other signal. Delay times are generally expressed as a range (e.g. 5-10 ns) because there is some uncertainty associated with high volume component manufacture and circuit operating conditions. Delay times are given to the designer by the chip component manufacturer. Traditionally, designers have assumed that the entire uncertainty range for each component should be accounted for independently of the other delays. Therefore, the time difference between any two delays must be calculated assuming that one is at its maximum time and the other at its minimum time. This forces the design to meet a worst-case analysis where the most conservative clock speed is chosen.
However, it is known that components placed on the same circuit have some correlation between their delay times. If one component has an actual delay time at the high end of its uncertainty range, others on the same circuit will tend to be at the high end also. This results from similarities in the manufacturing process used to make the gates, similar operating temperature, and physical proximity. Chip manufacturers are beginning to publish this type of correlation information in their design handbooks. This data is furnished in terms of a correlation factor between two gates, i.e. a percentage or a fraction between 0-1. It is determined by empirical measurements of the delay speeds for gates in a circuit.
Delay correlation allows a better than worst-case analysis to be used in design. This is because correlated gates have a reduced time difference between their outputs. This reduction can be thought of as a time savings which can, in turn, be translated into a corresponding increase in clock speed.
A simple example will better illustrate the concept of delay correlation.
FIG. 1
shows two gates each having some propagation delay range. D
1
ranges from 5-10 ns and D
2
ranges from 0-5 ns. If the two gates have no delay correlation (the usual assumption) then the actual delay times for each could fall anywhere in the shown ranges. For instance, if D
1
=10 ns, then D
2
could have a delay time as low as 0 ns. We will call this condition 0% correlation.
At the other end of the spectrum is 100% correlation. This means that if D
1
=5 ns, then D
2
=0 ns. If D
1
=7.5 ns then D
2
will be at 2.5 ns, and so forth. Clearly 100% correlation greatly reduces the difference between the two delays.
What happens for, say, 80% correlation? If D
1
=5 ns, then D
2
will be in the range 0-1 ns. In other words the possible range for D
2
spans 20% (100%-80%) of its total range. Now, if D
1
=10 ns, then D
2
would have a range of delay times from 4-5 ns. This is because the D
2
range is ±20% around 5 ns, it's corresponding point. Obviously, since a higher delay time than 5 ns is not possible, the range is 4-5 ns rather than 4-6 ns.
By inspecting the table in
FIG. 1
we can calculate the minimum and maximum differences between the delays for each correlation factor. For 0% correlation, the difference works out to 0-10 ns, for 100% it is exactly 5 ns, and for 80% it is 4-6 ns. These numbers, tabulated in
FIG. 1
, illustrate the effect of delay correlation on time differences between events.
The change in these differences as correlation factor increases allows for a faster circuit design. For 100% correlation, the designer knows that D
1
will always arrive 5 ns after D
2
. For 0%, D
1
could arrive as much as 10 ns after D
2
. The uncorrelated circuit is, in effect, 5 ns slower than the perfectly correlated one.
The differences given in
FIG. 1
can be arrived at through two equations. The first expresses the minimum time of arrival of D
1
with respect to D
2
:
&Dgr;
min
=a
1
−b
2
+min[(
b
1
−a
1
),(
b
2
−a
2
)]
cf
(1)
The second expresses the maximum time of arrival of D
1
with respect to D
2
:
&Dgr;
max
=b
1
−a
2
−min[(
b
1
−a
1
),(
b
2
−a
2
)]
cf
(2)
Note that negative answers indicate that D
1
arrived before D
2
. Also note that by reversing the sign on each equation, we obtain the time of arrival of D
2
with respect to D
1
.
Given the benefits of delay correlation, it is the purpose of this invention to incorporate a general method for calculating it into computer programs for timing analysis. Although variations on the concept have been incorporated into other timing analysis products, none has done so in the general manner that is proposed here. To confirm this point, a review of the prior art will now be made.
Several timing analysis software packages are and have been available on the open market. The first such product was called dV/dt® by Engineerium™, a company no longer doing business. The product featured a windowed environment where the user could graphically create timing diagrams and analyze the corresponding timing relationships. No features existed where delay correlation relationships could be entered or calculated, so the product based its timing analysis on a worst-case scenario.
U.S. Pat. No. 5,576,979 refers to another such product by Chronology™ Corp., known as TimingDesigner®. This product also includes a windowed timing diagram editing environment, but in addition has a feature which enables signal skews to be included in the analysis. This feature was developed in attempt to model delay correlation in a specific situation, the case of clock buffers. Because data sheets commonly attach a parameter called skew which related two signals of the buffer, Chronology added a feature to allow entry of a skew value and associated computation to adjust for the reduction of uncertainty between output edges in this particular case. This modeling technique has a serious flaw, however. In particular, signal skews as used in the U.S. Pat.
Menegay Peter
Notestein Daniel L.
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