Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-25
2002-06-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06412095
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for wiring layout and an apparatus for automating wiring layout in semiconductor integrated circuit devices, and more particularly, to a wiring layout method and an automated wiring layout apparatus that compacts and arranges wires efficiently.
In semiconductor integrated circuit devices, the increase in the amount of data and the number of bits for each data word has increased the number of signal wires that connect logic modules. Therefore, it is desirable that the signal wires be arranged efficiently to realize higher integration and higher processing speed of the semiconductor integrated circuit devices.
FIG. 1
shows an arrangement of modules
22
on a semiconductor substrate
21
. The designing of a semiconductor integrated circuit device
20
involves determining the area allocated for each module
22
arranged on the substrate
21
, forming a circuit element in each module
22
, and placing and connecting the modules
22
. Connecting the modules
22
, or wiring layout, includes the process of laying out signal wires
23
and power wires between the modules
22
.
Layout of the signal wires
23
is especially complicated and burdensome since the signal wires
23
must be arranged in a limited area, preferably with minimum wire lengths. In addition, high integration of the semiconductor integrated circuit device
20
has resulted in multilayer signal wires
23
. This has caused the wiring layout of the signal wires
23
to be further complicated and thus further burdensome.
An automated wiring layout apparatus provided with a computer aided design tool is used to accomplish efficient and accurate wiring layout within a short period of time. A typical automated wiring layout apparatus processes an actual wiring pattern laid out by an operator to generate a wiring pattern having minimized wiring length and wiring volume.
FIG. 2
shows an actual pattern of a prior art wiring layout.
FIG. 3
shows an actual pattern of a compacted wiring layout generated by compacting the wiring layout of
FIG. 2
with a conventional automated wiring layout apparatus. As shown in
FIG. 2
, a first wiring L
1
is formed by a lower layer wire LA
1
a
, an upper layer wire LB
1
a
, and a contact CT
1
a
. A second wiring L
2
is formed by three lower layer wires LA
2
a
, LA
2
b
, LA
2
c
, two upper layer wires LB
2
a
, LB
2
b
, and four contacts CT
2
a
, CT
2
b
, CT
2
c
, CT
2
d
. A third wiring L
3
is formed by a lower layer wire LA
3
a
, an upper layer wire LB
3
a
, and a contact CT
3
a.
The automated wiring layout apparatus identifies lower layer wires of other wirings that extend between the lower layer wires LA
2
a
and LA
2
c
. The layout apparatus then connects the lower layer wires LA
2
a
, LA
2
c
with a new lower layer wire, as shown in FIG.
3
. This results in the second wiring L
2
being formed by a single lower layer wire LA
2
x
. Accordingly, the lower layer wire LA
2
b
, the two upper layer wires LB
2
a
, LB
2
b
, and the four contacts CT
2
a
, CT
2
b
, CT
2
c
, CT
2
d
become unnecessary. This shortens the wiring length and decreases the wiring volume of the second wiring L
2
. In addition, since the space that would be used for the lower layer wire LA
2
b
and the contacts CT
2
b
, CT
2
c
becomes free, the length of the actual pattern shown in
FIG. 2
in the vertical direction is shortened. That is, a compacted actual pattern is obtained. This enables the other wirings to be routed with less restrictions.
However, the prior art layout apparatus has limitations to the compacting of the wirings.
FIG. 4
shows an example of such a limitation. An actual pattern of wirings illustrated in
FIG. 4
includes a first wiring L
1
formed by a lower layer wire LA
1
a
, an upper layer wire LB
1
a
, and a contact CT
1
a
. A second wiring L
2
is formed by three lower layer wires LA
2
a
, LA
2
b
, LA
2
c
, two upper layer wires LB
2
a
, LB
2
b
, and four contacts CT
2
a
, CT
2
b
, CT
2
c
, CT
2
d
. A third wiring L
3
is formed by a lower layer wire LA
3
a
, an upper layer wire LB
3
a
, and a contact CT
3
a
. A fourth wiring L
4
is formed by a lower layer wire LA
4
a
, an upper layer wire LB
4
a
, and a contact CT
4
a
. To form the second wiring L
2
with a single lower layer wire, the layout apparatus identifies the fourth wiring L
4
(lower layer wire LA
4
a
) as an obstacle. Therefore, the layout apparatus determines that further compacting is not possible. In this case, the operator must manually layout the wiring to further compact the actual pattern of FIG.
4
. Such manual intervention requires a great amount of time.
Accordingly, it is an objective of the present invention to provide a method for compacting wiring layout and an apparatus for automated wiring layout that have enhanced compacting efficiency.
SUMMARY OF THE INVENTION
Briefly stated the present invention provides a method for compacting a wiring layout pattern. The pattern includes at least a first wiring and a second wiring, each wiring having a plurality of first layer wires extending in a first direction and a plurality of second layer wires extending in a second direction generally perpendicular to the first direction Two first layer wires of the same wiring are arranged at different locations and are connected to each other by a second layer wire. The method includes the steps of: a) identifying first layer wires of other wirings that interfere with a line extending from one of the two first layer wires in the first direction; b) forming an enlarged area between the obstructed first layer wire and the interfering first layer wire of the other wiring; c) shifting the other one of the two first layer wires to the enlarged area to be aligned along the same line with the obstructed first layer wire; d) setting the original layout area of the other one of the two first layer wire as an open area; and e) deleting the second layer wire previously connecting the two first layer wires.
The present invention also provides a method for compacting a wiring layout pattern including the steps of: a) searching for an open first area to which one of the two first layer wires of the same wiring is moved in the second direction without interfering with first layer wires of other wirings, wherein the second layer wire connecting the two first layer wires is not interfered with by second layer wires of other wirings; b) moving the one of the two first layer wires to the open area; c) extending the second layer wire connecting the two first layer wires in the second direction; and d) connecting the extended second layer wire with the moved first layer wire.
The present invention further provides a method for compacting a wiring layout pattern including the steps of: a) searching for an open area to which a first portion of one of the two first layer wires of the same wiring is moved in the second direction without interfering with first layer wires of other wirings; b) setting a layout prohibition area around a second layer wire of other wirings either if the second layer wire of the other wiring is located on a line extending from the second layer wire connecting the two first layer wires or if the second layer wire of the other wiring is located closer to the open area; c) setting a route to the open area for the second layer wire to be moved by bypassing the prohibition area, wherein the bypass route permits the layout of the second layer wire in the first direction and the second direction; d) moving the first portion of one of the two first layer wires to the open area; e) extending the second layer wire connecting the two first layer wires along the bypass route; and f) connecting the extended second layer wire to the moved first portion.
The present invention provides a method for producing semiconductor integrated circuit devices. The method includes the step of generating exposure data for first layer wires and second layer wires using a compacted wiring layout pattern generated by: a) identifying first layer wires of other wirings that interfere with a l
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Smith Matthew
Thompson A. M.
LandOfFree
Method and apparatus for compacting wiring layout does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for compacting wiring layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for compacting wiring layout will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2923912