Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-09
1999-07-27
Sheikh, Ayaz R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395292, 39580001, 395822, 395728, 39520042, 395856, 395306, 395309, 711123, 711146, 711157, 370412, G06F 1314
Patent
active
059304839
ABSTRACT:
A method and apparatus are provided for controlling communications on a small computer system interface (SCSI). A cache memory is arranged for storing an input queue, a status queue and a cache operation queue. An input engine detects unsolicited data from the SCSI and transfers the detected unsolicited data to the input queue. A status engine transfers status information between the SCSI and the status queue. A cache engine transfers data between the SCSI and the cache operation queue. Each of the input engine, the status engine, and the cache engine is independent to enable full duplex operation. A connection arbitrator is shared between the input engine, the status engine, and the cache engine enabling a connection to be shared by the input engine, the status engine, and the cache engine.
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Cummings Peter Allen
Morger Brian Lee
Rolls Richard
Yonker Teras Eve
International Business Machines - Corporation
Jean Frantz Blanchard
Pennington Joan
Sheikh Ayaz R.
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