Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Reexamination Certificate
2000-04-11
2003-05-27
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
C712S215000, C710S040000, C710S112000, C709S241000, C709S241000, C711S145000, C711S156000, C711S220000
Reexamination Certificate
active
06571332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to system memory transactions.
2. Description of the Related Art
In general, computer systems include a microprocessor, system memory, a video graphics adapter and a plurality of peripheral devices. The memory and peripheral devices are typically coupled to the microprocessor through one or more system buses. In personal computers (PCs), these buses are controlled by bridging logic and controllers which may be separated into different integrated circuits: The system controller and the peripheral bus controller. The system controller, commonly referred to as a northbridge in PC systems, includes bridging logic, a memory controller and an accelerated graphics port (AGP) controller and a peripheral bus controller.
Many peripheral devices and the graphics port commonly need access to the system memory through the memory controller. Typically, theses devices request memory accesses or transactions in a particular order, but receive the transaction responses in a different order. Therefore the various peripheral controllers and the graphics port controller must use some method of keeping track of which responses correspond to which requests. One method of keeping track of the requests and responses is to attach a linearly incrementing tag to each request. A request tag table is then used to store the request tags. As the responses come back, they can be sorted and reordered by matching the response tags with the request tags in the request tag table. The reordered responses can then be stored in a response buffer. Additional logic, such as a free buffer space counter, may be employed to prohibit the response buffer from being overflowed by not allowing requests to issue while the response buffer is full. Additional methods may employ a large enough response buffer that the free buffer space counter is not necessary.
Although the above methods may provide a method of reordering transactions and keeping track of which responses correspond to which requests, it is desirable to use a different method to provide buffer reordering and management.
SUMMARY OF THE INVENTION
The problems outlined above may in large part be solved by a method and apparatus for transaction reordering and buffer management. In one embodiment, the apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is coupled to the memory controller and is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is coupled to the first generator circuit and is configured to generate a second tag using the size of said first memory request added to the first tag.
In an additional embodiment, the first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request. The second generator circuit may be further configured to generate a third tag using the size of the second memory request added to said second tag.
The generation of transaction requests encoded with tags which correspond to addresses in the transaction response buffer based on the size of the requested transaction may advantageously simplify the process of reordering memory transaction responses.
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Ennis Stephen C.
Hewitt Larry D.
Miranda Paul C.
Advanced Micro Devices , Inc.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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