Method and apparatus for collision-free data transfers in a memo

Details Method and apparatus for collision-free data transfers in a memo Method and apparatus for collision-free data transfers in a memo

1997-07-10

2000-03-28

Peikari, B. James

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 45, 710 38, 710130, 710240, G06F 13376

Patent

active

060444290

ABSTRACT:
A synchronous dynamic random access memory ("SDRAM") operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

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