Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1994-11-08
1996-03-26
Hudspeth, David R.
Electronic digital logic circuitry
Interface
Logic level shifting
326 71, H03K 190175
Patent
active
055024050
ABSTRACT:
A translator for translating signals from a CML or ECL circuit to signals that are compatible with CMOS or TTL voltage levels is disclosed. The translator has minimum power consumption and provides switching and drive characteristics that are independent of the threshold voltage, power supply voltage, temperature and process variations. The translator includes the following components: a bias reference generator for receiving a first bias voltage and generating a second bias voltage; an input circuit for receiving the input signals; a cascode circuit for receiving the second bias voltage, having a controlled current and outputting the output signals; and a current-mirror circuit. The first bias voltage is at the mid-point of the logic swing of the input signals, and the bias reference generator provides the second bias voltage to generate the controlled current in the switching stage of the translator. A method for translating signals having CML or ECL logic voltage levels to signals having CMOS or TTL logic voltage levels includes the following steps: receiving a first bias voltage that is substantially in the mid-point of the logic swing of the input signals; providing a second bias voltage to a cascode circuit for producing a controlled current in the cascode circuit; receiving the input signals; switching the cascode circuit; and producing the output signals.
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Cypress Semiconductor Corporation
Hudspeth David R.
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