Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-10-29
2004-01-20
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000
Reexamination Certificate
active
06680989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for clock switching, and more particularly to a method and apparatus for switching a clock extracted from a transmission line signal in a digital transmission apparatus or a digital exchange.
2. Description of the Related Art
Remote transmission apparatuses, unlike transmission apparatuses installed within a central office, are often located in areas where there are no apparatuses nearby that supply reference clocks. To address this, a method has been developed that creates a reference clock from the clock extracted from a transmission line signal (transmission line extracted clock) received from a distant location.
In this type of remote transmission apparatus, the reference clock for use within the apparatus is created by selecting one of transmission line reference clocks received from two transmission lines, line
0
and line
1
, and by supplying the selected clock to a PLL circuit. However, the PLL is sensitive to the switching of the input source and, depending on the phase difference between the two clocks, an unexpected situation, such as the generation of an erroneous alarm, may occur. Usually, such a problem is addressed, for example, by varying a PLL circuit constant (lock capture time).
However, while the problem can be addressed to a certain extent by varying the PLL circuit constant, it is often difficult to improve the characteristics of the PLL circuit for the following reasons.
Both the recapture time and frequency disturbance characteristics cannot be improved at the same time; therefore, one or the other of the characteristics must be sacrificed.
If the input frequency to the PLL circuit is extremely low, it takes a long time before the PLL can acquire lock and then settle.
SUMMARY OF THE INVENTION
The present invention has been devised in view of the above situation, and it is an object of the invention to provide a clock switching system that can suppress clock disturbances when a standby clock is switched to an active clock.
According to the present invention, there is provided a clock switching method comprising the steps of: selecting one of a plurality of clocks and generating a reference clock from the selected clock; detecting a phase difference between the clock before the selection and the reference clock; and changing the phase of a non-selected clock based on the detected phase difference so that a phase difference from the selected clock is reduced, and thereby suppressing clock disturbances when the clock selection is switched.
According to the present invention, there is also provided a clock switching apparatus comprising: a clock selection and reference clock generation circuit for selecting one of a plurality of clocks, and for generating a reference clock from the selected clock; a phase difference detector for detecting a phase difference between the clock before the selection and the reference clock; and a phase changing section for changing the phase of a non-selected clock based on the detected phase difference so that a phase difference from the selected clock is reduced, and thereby suppressing clock disturbances when the clock selection is switched.
REFERENCES:
patent: 5455840 (1995-10-01), Nakauchi et al.
patent: 5528198 (1996-06-01), Baba et al.
patent: 5920600 (1999-07-01), Yamaoka et al.
patent: 6044122 (2000-03-01), Ellersick et al.
patent: 57-57327 (1982-04-01), None
patent: 08097750 (1996-04-01), None
Katten Muchin Zavis & Rosenman
Vo Don N.
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