Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-06-15
2001-02-20
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C713S503000, C714S700000
Reexamination Certificate
active
06192092
ABSTRACT:
FIELD
The present invention relates to clock signals. More particularly, the present invention relates to a method and apparatus to compensate for skew in a clock signal. BACKGROUND
A processor comprises an integrated circuit, or chip, with a large number of elements that perform various logical functions, such as mathematical operations. Within the processor, a clock signal, also known as a “global” clock signal, is used to synchronize data operations performed by elements positioned at different locations on the chip. For example, an element at one location may indicate that information will be available in an internal register during the next global clock cycle. By using the same global clock signal, an element at another location may read the information from the register at the appropriate time. As processor speed has increased, the frequency of the processor's global clock signal has also increased. Clock signals operating at a frequency of 300 million cycles per second (300 MHz) are now common, and will likely increase in the future.
The performance of a processor is based, at least in part, on the synchronization of the global clock signal throughout the chip. For example, it is desirable that information stored in a register is not read before the information has been correctly updated. Moreover, waiting too long before reading the information will usually slow down the operation of the processor. Thus, it is desirable to have the global clock signal arrive at different locations, or destinations, as close to simultaneously as possible.
With the increase in global clock frequency, however, clock inaccuracy has become a large problem in processor design. Clock inaccuracy results in one clock edge not arriving at a sampling point at its nominal time, measured relative to another clock edge. One type of clock inaccuracy is commonly referred to as clock “skew.” Consider, for example, two clock signals A and B generated from a single input signal, as shown in FIG.
1
A. As can be seen, both paths have an equal number of inverters
10
which should nominally cause the input clock signal to experience a substantially equal delay, T
0
, along both paths. Suppose, however, that the two paths are laid out on two distant locations on the chip. Assume also that the inverters
10
in path B are laid out next to large bus drivers with high activity factors, so that the supply voltage is lower than that for the devices in path A, which neighbor only small gates with low activity factors. In addition, assume that the channel lengths in path B are actually longer than expected because of some optical defects in the lens used to create the chip, or for other reasons, while the lengths in path A are unaffected. As shown in
FIG. 1B
, these factors will cause the delay through path B, T
B
, to be longer than the designed nominal T
0
. Similarly, the delay through path A, T
A
, will be shorter than T
0
. The difference between the two clock signals, or “skew,” is also shown in FIG.
1
B.
A number of factors may cause the global clock signal in a processor to be skewed at different locations on the chip. For example, variations in the effective channel length of devices across the chip may occur because of in-die variations resulting from lens distortion, wafer planarity or stepper accuracy. Local effects, like device proximity, may also result in variations in channel length. Supply voltage variations across the chip may likewise cause skew, depending on the power grid design and proximity to high activity or large devices. Moreover, Inter-Layer Dielectric (ILD) thickness variation, causing variations in interconnect capacitance, and signal coupling to neighboring lines, may result in delay variation. Also, a design error, such as a mistake when modeling a portion of a circuit, may also contribute to skew.
Several methods of reducing global clock skew are well-known. For example, designers strive to reduce the part of the path that is different between two clock signals. Because each portion, or “stage,” which is different may contribute to the clock skew, reducing the number of stages which are different may reduce the clock inaccuracy. Clocks which are logically the same may also be tied together when they are physically close, and a common node is no more than two or three stages back. Additionally, attempts have been made to reduce signal coupling to clock lines, but this generally involves increased line spacing or the insertion of shielding wires. All of these solutions have become less effective with the increase in processor clock frequency. Moreover, the methods have become more difficult because the number of elements in a single processor has increased dramatically over the years.
In view of the foregoing, a need exists for a method and apparatus for deskewing a clock signal to improve synchronization within a processor, and solving the other problems discussed above.
SUMMARY
In accordance with an embodiment of the present invention, a distributed clock signal at a first location in a processor is compared with a reference clock signal. The distributed clock signal is corrected based on the results of the comparison with the reference clock signal.
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Barkatullah Javed S.
Dizon Rommel O.
Fletcher Thomas D.
Rosen Eitan
Chin Stephen
Intel Corp.
Jiang Lenny
Kenyon & Kenyon
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