Method and apparatus for clock skew calibration in a clock...

Details Method and apparatus for clock skew calibration in a clock... Method and apparatus for clock skew calibration in a clock...

2006-09-28

2010-11-30

Payne, David C (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

07844021

ABSTRACT:
Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of “early” and “late” corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

REFERENCES:
patent: 4074358 (1978-02-01), Caputo et al.
patent: 6560304 (2003-05-01), Yoon et al.
patent: 2003/0123591 (2003-07-01), Walker
patent: 2004/0030513 (2004-02-01), Kocaman et al.
patent: 2005/0163272 (2005-07-01), Payne et al.

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