Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2003-06-12
2004-11-23
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S094000, C326S095000
Reexamination Certificate
active
06822481
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to clock gating circuits, and in particular to methods for gating clock distribution networks within digital circuits.
2. Description of Related Art
Digital circuits have widespread applications in the computing industry. Recently, the demand for mobile computing devices, such as personal digital assistants (PDAs), cellular telephones and laptop computers, has increased significantly. Mobile computing devices typically rely on batteries for power, and therefore, a key specification for such devices is low power consumption. In addition to increasing the battery life, reducing the power consumption in mobile computing devices also reduces the amount of heat generated, which enables smaller computing devices to be produced with diminished cooling requirements.
Significant power savings in such mobile computing devices can be obtained by reducing the amount of switching activity in the digital circuitry. In most digital circuit designs, the clock distribution network or “tree” includes a large number of switching elements to distribute the clock signal to all functional blocks (e.g., logic components) of the circuit with minimal clock skew. To reduce the power consumption of the clock distribution network, various “clock gating” methods have been utilized to prevent functional blocks from receiving a clock signal while in an idle state.
For example, U.S. Reissue Pat. No. Re. 36,839 to Simmons et al. and U.S. Pat. No. 6,232,820 to Long et al., each of which is hereby incorporated by reference, both describe conventional clock-gating circuits that enable and disable the clock signal to functional blocks in a digital circuit. However, neither Simmons et al. nor Long et al. address the power dissipation resulting from the switching elements within the clock tree feeding the functional blocks. Thus, conventional clock-gating circuits do not sufficiently reduce the power consumption in digital circuits.
Other efforts at improving the clock tree efficiency with gated clocks also have not adequately or effectively reduced the power consumption in traditional digital circuits. For example, U.S. Pat. No. 6,272,667 to Minami et al., which is hereby incorporated by reference, proposes a CAD tool to insert and optimize the buffer cells that are placed after the clock-gating enable signal is generated. As another example, U.S. Pat. No. 6,434,704 to Dean et al., which is hereby incorporated by reference, describes an algorithm to separate the gated and ungated clock tree, while also minimizing the clock skew. Both Minami et al. and Dean et al. present complicated circuit design techniques that are not easily implemented into existing digital circuits. Therefore, neither Mianami et al. nor Dean et al. provide a suitable solution for reducing power consumption requirements in traditional digital circuits. Thus, what is needed is a clock gating system for gating the clock tree to individual functional blocks of a digital circuit.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a clock gating circuit for use in a digital circuit having at least one functional block. The clock gating circuit gates the clock signal at an input to a clock tree feeding the functional block. The clock gating circuit includes a logic gate that receives both a clock signal and a clock disable signal generated by the functional block. Based on the value of the clock disable signal, the logic gate gates the clock signal to the functional block.
In one embodiment, the functional block generates the clock disable signal while in an idle state. The functional block determines whether the next operating state is an idle state based upon the current state and the value of the input signals to the functional block. Each functional block includes combinational logic and one or more clocked external flip-flops. The clock disable signal gates the clock signal to the external flip-flops to prevent switching of the external flip-flops. In addition, the clock disable signal gates the clock signal to any internal flip-flops within the functional block to further reduce power consumption in the digital circuit.
In further embodiments, the digital circuit is a pipeline circuit having multiple functional blocks interconnected in a pipeline design. Each functional block generates a respective clock disable signal to gate the clock signal to each functional block independently of other functional blocks within the pipeline. Additional embodiments include a global signal generator for providing a global signal to each of the functional blocks to prevent the generation of clock disable signals, when necessary, such as during testing of chips.
REFERENCES:
patent: 5923188 (1999-07-01), Kametani et al.
patent: RE36839 (2000-08-01), Simmons et al.
patent: 6204695 (2001-03-01), Alfke et al.
patent: 6232820 (2001-05-01), Long et al.
patent: 6247134 (2001-06-01), Sproch et al.
patent: 6272667 (2001-08-01), Minami et al.
patent: 6434704 (2002-08-01), Dean et al.
Clark, II Airell Richard
Srikantam Vamsi K.
Agilent Technologie,s Inc.
Tran Anh Q.
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