Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2006-11-28
2006-11-28
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S047000, C327S298000
Reexamination Certificate
active
07142008
ABSTRACT:
According to one example embodiment, a complex, programmable logic device (CPLD-type) has logic blocks and Input/Output (I/O) pads interconnected via a programmable interconnect array. A dedicated logic block is directly coupled to I/O pads, which provides external access to the dedicated logic block without traversing the programmable interconnect array. The dedicated logic block may include a clock divider module for providing a divided clock to the CPLD.
REFERENCES:
patent: 5302866 (1994-04-01), Chiang et al.
patent: 6218876 (2001-04-01), Sung et al.
Altera Corporation; “Using the ClockLock and ClockBoost PLL Features”; Application Note 116; Nov. 2003, ver 2.6; available from Altera Corporation at http://www.altera.com/literature/lit-an.jsp; pp. 1-56.
Xilinz, Inc.; “Using the Virtex Delay-Locked Loop”; XAPP132 (2.8) Jan. 5, 2006; available from Xilinx, Inc. at http://www.—xilinx.com/xlnx/xweb/xil—publications—showall.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1209827&iLanguageID=1; pp. 1-16.
Cho James H.
Kanzaki Kim
Maunu LeRoy D.
Xilinx , Inc.
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