Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2011-03-22
2011-03-22
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S322000, C327S175000
Reexamination Certificate
active
07913103
ABSTRACT:
A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
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Eaton Craig D.
Gold Spencer M.
Kwan Bill K. C.
Globalfoundries Inc.
Heter Erik A.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Suryawanshi Suresh K
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