Cleaning and liquid contact with solids – Processes – For metallic – siliceous – or calcareous basework – including...
Reexamination Certificate
2000-07-18
2001-11-20
Carrillo, Sharidan (Department: 1746)
Cleaning and liquid contact with solids
Processes
For metallic, siliceous, or calcareous basework, including...
C134S022190, C134S025400, C134S026000, C134S034000, C134S036000, C134S042000, C134S902000, C510S175000, C015S022100, C015S077000, C015S088300, C015S102000
Reexamination Certificate
active
06319330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the cleaning of semiconductor wafers, and, more particularly, to techniques for cleaning wafers having hydrophobic low k dielectric and metal surfaces.
2. Description of the Related Art
Integrated circuits utilize dielectric layers to insulate conductive lines on various layers of a semiconductor structure. However, as circuits become faster and more compact, the distances between the conductive lines decrease, which necessarily introduces increased coupling capacitance. Therefore, it has become increasingly important to have a dielectric layer that is able to better insulate conductive lines against the increasing coupling capacitance levels, which have the drawback of slowing the operation of the semiconductor device.
FIG. 1A
is a cross-sectional view illustrating several layers of a typical prior art integrated circuit
10
. The integrated circuit
10
includes a substrate
12
that supports an oxide dielectric layer
14
, which is typically silicon dioxide (SiO
2
). A metal layer typically made of aluminum (Al) is deposited onto the oxide dielectric layer
14
and etched into a plurality of metal lines
16
. For ease of illustration, only two metal lines
16
are shown, but as is well known in the art, many additional metal lines
16
are used to provide the necessary interconnections of a layer of an integrated circuit device.
Generally, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant (K) of the dielectric material used. The oxide dielectric layer
14
, which is typically made from silicon dioxide, has a dielectric constant of about 4.0. Because line densities and operating frequencies in semiconductor devices are constantly increasing, the coupling capacitances between conductive lines have increased to the point that the oxide dielectric layer
14
having a dielectric constant of about 4.0 is a less than adequate insulator.
FIG. 1B
is a cross-sectional view illustrating several layers of another type of prior art integrated circuit
20
incorporating an organic dielectric layer
22
. The organic dielectric layer
22
typically has a dielectric constant of between about 1.5 and about 3.5. Thus, the organic dielectric layer
22
is much less conductive than the oxide dielectric layer
14
and better able to isolate conductive lines and reduce the coupling capacitances. After the organic dielectric layer
22
is formed over the substrate
12
, a plurality of trenches
24
is etched into the organic dielectric layer
22
. Then, the trenches
24
are filled by depositing a copper (Cu) layer
26
(or aluminum) over the organic dielectric layer
22
.
FIG. 1C
illustrates the integrated circuit
20
of
FIG. 1B
after a conventional chemical mechanical polishing (CMP) operation is performed. The CMP process planarizes the top surface of the copper layer
20
down to the organic dielectric layer
22
and the resulting copper lines
28
. However, the CMP process leaves behind a film of particles and metal contaminants (“contaminants”)
30
on the surface of the dielectric layer
22
and the copper lines
28
. As is well known in the art, copper has a lower resistance than the aluminum used in the integrated circuit
10
of FIG.
1
A. However, copper is also known to be more susceptible to corrosion than aluminum, which makes it even more important to clean contaminants
30
from its surface.
FIG. 1D
illustrates another partial view of a prior art semiconductor device
40
where the organic dielectric layer
22
is spun on or deposited by chemical vapor deposition (CVD).
FIG. 1E
illustrates another partial view of a prior art semiconductor device
50
after a via hole
52
is etched through a dielectric layer
54
down to a metal line
56
. In both the semiconductor devices
40
and
50
, the spin-on/deposition and via hole etch leave behind a film of contaminants
30
.
In the integrated circuit
10
of
FIG. 1A
, any particles were capable of being cleaned by simply, e.g., spraying the surface of the oxide dielectric layer
14
with aqueous solutions such as de-ionized water, or de-ionized water and acid/base. As is well known, cleaning the particles from the surface of silicon dioxide type dielectrics is rather straight forward because this kind of material is substantially hydrophilic. That is, when cleaning fluids are applied to the surface of a hydrophilic material, the fluids will actually wet over the surface. To further facilitate cleaning, some cleaning processes implement a special polyvinyl alcohol (PVA) brush (i.e., a very soft sponge) to assist in dislodging the particles, using de-ionized water and/or acid/base. The particles would then be removed from the surface of the silicon oxide dielectric layer when rinsed off.
Unfortunately, this conventional method of cleaning the semiconductor wafer does not work for semiconductor devices that incorporate low K dielectric polymers and/or organic dielectric materials, such as the organic dielectric layer
22
. Organic dielectric materials are hydrophobic, therefore, the cleaning fluids are repelled from the surface of the organic materials. As is well known, a contact angle may be measured from a droplet of water that is in direct contact with a given material to determine the degree of repulsion.
In addition, organic dielectric materials are chemically inert, which prevent them from reacting with chemical reagents to convert hydrophobic surfaces into hydrophilic surfaces while leaving the bulk materials intact. Because standard cleaning fluids fail to achieve sufficient contact with the hydrophobic organic dielectric materials, scrubbing the semiconductor wafer with a brush would only draw more particles to the surface of the wafer. Therefore, using scrubbing techniques over hydrophobic organic surfaces will only exacerbate the particle contamination problem. As is well known, some hydrophobic organic surfaces can be cleaned using organic solvents. However, such organic solvents are often highly toxic and more expensive than water. Further yet, when the toxic organic solvents are used, more complex equipment is required to perform the cleaning processes. The brush material, PVA, is, in general, not compatible with organic solvents. As a result, cleaning using organic solvents is highly undesirable.
In view of the foregoing, it is desirable to have an apparatus and method of cleaning particles and/or metal contaminants from hydrophobic organic dielectric layers using aqueous solutions without damaging the integrated circuit surface.
SUMMARY OF THE INVENTION
The present invention fills these needs by providing an efficient and economical method and apparatus for cleaning low K dielectric polymer surfaces (organic and inorganic) and metallization surfaces of a wafer without damaging the integrated circuit device surface. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment of the present invention a method for cleaning a low K dielectric film surface of a semiconductor substrate is disclosed. The method includes applying de-ionized water and a surfactant formulation solution to the low K dielectric polymer surface to form a wettable conditioning layer. The wettable conditioning layer is configured to commence the cleaning that is targeted to remove particle and/or metal contaminants throughout the low K dielectric polymer surface. To continue the cleaning, de-ionized water and a surfactant solution are applied over the low K dielectric polymer surface. The semiconductor substrate then is spin-rinsed to remove any applied surfactant formulation solution or surfactant solution while removing the remaining particle contaminants and/or metal contaminants from over the low dielectric polymer surface.
In another embodiment of the present invention an alternative method for cleaning
Hymes Diane J.
Jiang Linda (Tong)
Carrillo Sharidan
Lam Research Corporation
Martine & Penilla LLP
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