Method and apparatus for circuit partitioning and trace...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07844930

ABSTRACT:
Methods and apparatuses to design a circuit. In one embodiment, the method includes determining a first multiplexing ratio by a computer. The method, in one embodiment, further includes determining, according to the first multiplexing ratio, a first partition solution of the circuit and a first trace assignment solution for nets crossing partition boundaries of the first partition solution of the circuit. In one embodiment, the first trace assignment solution time multiplexes signals for a first plurality of nets crossing partition boundaries of the first partition solution according to the first multiplexing ratio, the first trace assignment solution satisfying a trace constraint, the first partition solution satisfying an area constraint when circuitry for time multiplexing signals for the first plurality of nets is considered.

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patent: 7107563 (2006-09-01), Kong
C. Fiduccia and R. Mattheyses, “A linear-time heuristic for improving network partitions”, In Proceedings of the Design Automation Conference, 1982.
Scott Hauck and Gaetano Borriello, “Logic Partition Orderings for Multi-FPGA Systems”, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 32-38, Feb. 1995.
Scott Hauck and Gaetano Borriello, “An Evaluation of Bipartitioning Techniques”, IEEE Trans. On CAD, vol. 16, No. 8, pp. 849-866, Aug. 1997.
Thomas H. Cormen, et al., “Introduction to Algorithms”, the MIT Press, Nineteenth printing, Chapter 27, pp. 579-629, 1997.

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