Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-06-13
2001-10-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06308305
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a method and an apparatus suitably used for circuit designing of a LSI, which has become larger in its size and more complex following an advance in a micro fabrication art in recent years.
2) Description of the Related Art
Generally, LSI designing is performed based on a procedure shown in FIG.
14
. This procedure includes steps as follows. First, logical designing is performed for a circuit (LSI) to be designed (step S
1
), then cells (circuit elements) are arranged based on the result of this logical designing (step S
2
) and a timing is checked for the result of this arrangement (step S
3
).
For a timing check, a delay value is calculated for each path while performing path tracing for the arranging result of the cells, and determination is made as to whether this value satisfies a timing condition or not. At this time, however, wiring has not beer decided yet among the cells. Thus, a delay value for each path is calculated by estimating a delay value which arises because of wiring (net) among the cells by using a Manhattan distance, and so on.
If the result of the timing check shows that there is an error path which does not satisfy the timing condition, arranging of the cells is performed again (from NO route of step S
4
to step S
2
). This rearranging of the cells (improvement of the arrangement) is repeated until the error path is canceled (until YES determination is made in step S
4
).
If the result of the cell arrangement satisfies the timing condition (YES determination is made in step S
4
), wiring is performed among the cells which have been arranged in step S
2
(step S
5
), and a timing check similar to that described above is also performed for this wiring result (step S
6
).
For this timing check, a delay value for each path is calculated based on an actual wiring length by performing path tracing for the wiring result among the cells, and determination is made as to whether the value satisfies the timing condition or not.
If the result of the timing check shows that there is an error path which does not satisfy the timing condition, wiring among the cells is performed again (from NO route of step S
7
to step S
5
). This rewiring (improvement of the wiring) is repeated until the error path is canceled (until YES determination is made in step S
7
). If the result of the cell arrangement satisfies the timing condition (YES determination is made in step S
7
), designing is finished.
On the other hand, if the timing condition is not satisfied even by the repeated rearranging or rewiring operation (no YES determination is made in step S
4
or S
7
), the process returns to step S
1
. Then, the process is started all over again from logical designing.
With an advance in a micro fabrication art in recent years, a LSI has become extremely large in its circuit size and complex. For this complicated circuit, a data timing problem must be solved among flip-flops (sequential circuit cells; referred to as FFs, hereinafter), which amount to a million and several hundred thousands in number.
Therefore, simple arranging of the cells or wiring among the cells without any indices is liable to lead to the occurrence of error paths. It is thus preferred that arranging or wiring should be efficiently performed by using. Certain indices for arranging or wiring so as to limit the generation of error paths as much as possible. For the improvement of arranging or wiring, it is also preferred that error paths are not simply improved, but rather these paths should be efficiently canceled (corrected) by using certain indices for improvements.
If logical designing is automatically performed based on logical synthesis while a circuit has become extremely large in its size and complexity, the number of gate stages among FFs may increase more than that expected by a designer. In this case, the designer recognizes a path (multi-stage path, and so on) having the unexpected number of gate stages among FFs as a critical path (path which is too short or too long) for the first time by a timing check (delay analysis), which is performed after arranging or wiring. However, even if the critical path is recognized at this time, it is difficult to cancel this critical path during rearranging or rewiring, and thus logical designing must be performed again. Consequently, a great increase occurs in the number of steps. Therefore, it is necessary to prevent the generation of unexpected multi-stage paths during logical designing.
Furthermore, during the correcting process of the arrangement or the wiring performed while the circuit size is large as described above, the degree of permissibility for changing the arrangement or the wiring becomes extremely small toward the end of packaging designing (including arranging, wiring, and so on), and accordingly it becomes difficult to make any changes. If an arrangement or wiring is changed for a spot which needs correction, other spots may be adversely affected, and in the worst case logical designing must be performed all over again. Consequently, a great increase may occur in the number of designing steps.
SUMMARY OF THE INVENTION
The present invention was made in order to solve the problems discussed above. It is a first object of the present invention to provide a method and an apparatus for circuit designing, whereby arranging and wiring are efficiently performed by using indices for arranging or wiring without the occurrence of any error paths.
The first object of the present invention is achieved by a circuit designing method, which comprises the steps of performing logical designing for a circuit to be designed, performing path tracing from one or more tracing start pins for the result of the logical designing when wiring is performed among cells after the cells are arranged based on the result of the logical designing, and counting the number of passing through each pin of the cells to be arranged during this path tracing.
In order to implement the circuit designing method described above, there is provided a circuit designing apparatus, which comprises a logical designing unit for performing logical designing for a circuit to be designed, an arranging unit for arranging cells based on the result of logical designing performed by this logical designing unit, a wiring unit for performing wiring among the cells arranged by this arranging unit, a path tracing unit for performing path tracing from one or more tracing start pins for the logical designing result of the logical designing unit, and a passing number counting unit for counting the number of passing through each pin of the cells to be arranged during path tracing performed by this path tracing unit.
With the circuit designing method and apparatus of the present invention, a passing number (static signal propagating density) of a path through each pin is calculated by performing path tracing after logical designing, and this passing number is used as an index for arranging or wiring. Accordingly, it is possible to perform arranging and wiring very efficiently by limiting the occurrence of error paths as much as possible.
It is a second object of the present invention to provide a method and an apparatus for circuit designing, whereby for the improvement of an arrangement or wiring, error paths are not simply improved but efficiently canceled by using certain indices for improvements.
The second object of the present invention is achieved by a circuit designing method, which comprises the steps of performing logical designing for a circuit to be designed, when wiring is performed among cells after the cells are arranged based on the result of this logical designing, performing path tracing from one or more tracing start pins for an arranging result or a wiring result, calculating a maximum value or a minimum value of an integrated delay value from one or more of the tracing start pins to each pin of the cells to be arranged through which a path passes during the path tracing, calculating degree of error importan
Abe Yasunori
Bizen Naomi
Sugiyama Hiroyuki
Do Thuan
Fujitsu Limited
Smith Matthew
Staas & Halsey , LLP
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