Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-15
2009-11-17
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07620927
ABSTRACT:
A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.
REFERENCES:
patent: 5436849 (1995-07-01), Drumm
patent: 5805861 (1998-09-01), Gilbert et al.
patent: 6102964 (2000-08-01), Tse et al.
patent: 6298319 (2001-10-01), Heile et al.
patent: 6490717 (2002-12-01), Pedersen et al.
patent: 6871336 (2005-03-01), Anderson
patent: 6996832 (2006-02-01), Gunduc et al.
patent: 7023744 (2006-04-01), Shimanek et al.
patent: 7086029 (2006-08-01), Barras et al.
patent: 7134112 (2006-11-01), Anderson et al.
patent: 7337100 (2008-02-01), Hutton et al.
patent: 7490312 (2009-02-01), Ochotta
patent: 2002/0162077 (2002-10-01), Jeng et al.
patent: 2004/0128626 (2004-07-01), Wingren et al.
patent: 2005/0172251 (2005-08-01), Chang et al.
patent: 2005/0240892 (2005-10-01), Broberg et al.
Ochotta, Emil S. etal., “Partition-Based Incremental Implementation Flow for Use with a Programmable Logic Device”, filed Aug. 8, 2006, U.S. Appl. No. 11/501,156, pp. available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Bell II, William R. et al., “Plug-In Component-Based Dependency Management for Partitions Within an Incremental Implementation Flow”, filed Aug. 8, 2006, U.S. Appl. No. 11/500,525, pp. available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Xilinx, Inc.; “Development System Reference Guide”; Chapter 3—Incremental Design; 2005; downloaded from http://toolbox.xilinx.com/docsan/xilinx7/books/docs/dev/dev.pdf; pp. 55-74.
U.S. Appl. No. 11/639,618, filed Dec. 15, 2006, Ochotta, Xilinx, Inc. 2100 Logic Drive, San Jose, CA.
U.S. Appl. No. 11/500,525, filed Aug. 8, 2006, Bell II et al, Xilinx, Inc. 2100 Logic Drive, San Jose, CA.
Leavesley, III W. Story
Ochotta Emil S.
Shiflet Eric M.
Stiehl William W.
Cuenot Kevin T.
Whitmore Stacy A
XILINX Inc.
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