Method and apparatus for circuit design

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07100138

ABSTRACT:
A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing. The protective routing also bridges the at least one port to inter-block routing connected to the net in a halo region. Software and/or a computer program product that can be used for multi-layer circuit design is also described.

REFERENCES:
patent: 5196362 (1993-03-01), Suzuki
patent: 5894165 (1999-04-01), Ma et al.
patent: 6182272 (2001-01-01), Andreev et al.
patent: 6189131 (2001-02-01), Graef et al.
patent: 6496968 (2002-12-01), Yamada et al.
patent: 6622293 (2003-09-01), Suzuki et al.

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