Etching a substrate: processes – Planarizing a nonplanar surface
Reexamination Certificate
1998-09-03
2002-01-22
Lund, Jeffrie R. (Department: 1763)
Etching a substrate: processes
Planarizing a nonplanar surface
C216S052000, C216S088000, C216S089000, C216S090000, C216S091000, C438S692000, C438S693000, C451S063000
Reexamination Certificate
active
06340434
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to methods and apparatuses for chemical-mechanical polishing (CMP) of an integrated circuit (IC) substrate. More particularly, the present invention relates to methods and apparatuses for a two stage chemical mechanical polishing (CMP) of an integrated circuit (IC) substrate surfaces and minimizing alignment shift that may occur during transferring of a circuit pattern from a reticle or a photomask to the IC substrate surface.
An IC, such as a semiconductor device is manufactured by forming circuits consisting of metal wiring on an IC substrate, e.g., a semiconductor substrate. The metal wiring forms an IC by connecting a plurality of discrete elements in the device with one another. Furthermore, the discrete elements in one layer are insulated from discrete elements in other layers of the device by a dielectric layer. In order to electrically connect one layer with another, one or more contact holes are formed through the dielectric layer and electrical connection is provided therethrough. As the degree of integration of VLSI's increases due to advances in technology, more and more wiring layers and discrete elements are increasingly required on the semiconductor substrate.
When metal wiring is formed on a substrate, the substrate surface is generally coarse and not very planar. However, when more than one layer containing discrete elements is employed to form an IC, it is important that the surface of each layer, including dielectric layers and wiring be made planar in order to accurately form contact holes and metal layers, improve the yield of the device and maintain the reliability of the final ICs. Particularly, when a circuit or wiring pattern from a reticle or photomask is transferred to the dielectric layer according to conventional photolithography, unless the dielectric layer is planar, it is difficult to accurately align the alignment tool above the IC substrate surface using alignment marks that may be formed in the conductive layer disposed below the transparent dielectric layer.
CMP is a planarization method currently employed to planarize substrate surface layers including dielectric layers and wiring. CMP typically involves mounting IC substrates face down on a substrate holder, e.g., wafer carrier, and rotating the IC substrate against a polishing pad mounted on a platen. A slurry containing a chemical that chemically interacts with the facing IC substrate layer and an abrasive, e.g., silica, alumina, cerium nitrate, that physically removes that layer is flowed between the IC substrate and the polishing pad or on the pad near the IC substrate. During CMP, both the substrate holder and the polishing pad typically rotate and the chemical condition, pressure, and temperature are controlled as the IC substrate contacts the polishing pad. The contents of the slurry may be chemically adjusted so as to optimize the chemical effects of CMP. Combination of chemical and physical effects of this polishing results in a significant planarization of the polished surface. The mechanical construction and the chemical ingredients of slurry used in CMP are widely known to those skilled in the art.
After being polished by CMP, the surface of an IC substrate is subjected to conventional photolithography to transfer the circuit or wiring pattern from a reticle to an IC substrate surface. In order to facilitate the transfer of the wiring pattern, an alignment tool aligns the placement of the reticle to alignment marks formed on the IC substrate such that the wiring pattern is transferred to the appropriate location on the IC substrate surface.
Unfortunately, when the dielectric layer is not planarized to the requisite amount, it is difficult to align using the alignment marks, which may be out of focus due to the nonplanarity of the dielectric layer. Consequently, there may be an alignment shift and the wiring pattern is not transferred to an appropriate location on the substrate surface.
What is therefore needed is a method and apparatus for CMP that inhibits alignment shift and transfers the wiring pattern to an appropriate location on the substrate surface.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides a method for chemical-mechanical polishing of a layer that is deposited on a surface of an integrated circuit substrate. The method includes: (1) immobilizing the integrated circuit substrate using a substrate holder such that the integrated circuit substrate surface is positioned against a surface of a polishing pad, which is mounted on a supporting surface; (2) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder allowing an endpoint of the chemical-mechanical polishing process of the layer to be detected; and (3) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface.
The method described above may further include introducing slurry on the polishing pad. The layer may be a conductive layer, e.g., tungsten, that is disposed above a dielectric layer. The integrated circuit substrate may be a semiconductor wafer and the substrate holder may be a wafer carrier. The supporting surface may be a polishing table or a platen. The rotational velocity of the polishing pad may be controlled by adjusting a rotational velocity of the supporting surface and the rotational velocity of the integrated circuit substrate surface may be controlled by adjusting a rotational velocity of the substrate holder. The second stage of polishing may include rotating both the polishing pad and the integrated circuit substrate surface in the same direction. The second stage of polishing may be carried out until the integrated circuit substrate surface is substantially planar and the substantially planar integrated circuit substrate surface facilitates alignment of an alignment tool above the integrated circuit substrate.
In the first stage of polishing, the endpoint of the chemical-mechanical polishing process of the layer may be detected by monitoring changes in current flow in a motor that is rotating the substrate holder. The first stage of polishing may include rotating both the polishing pad and the integrated circuit substrate surface in the same direction.
In another aspect, the present invention provides another method for chemical-mechanical polishing a layer deposited on a surface of a semiconductor wafer. The method includes: (1) immobilizing the semiconductor wafer using a wafer carrier pushing against a polishing pad that is mounted on a supporting surface; (2) supplying a polishing agent at the interface between the polishing pad and the semiconductor wafer; (3) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder such that an endpoint of the chemical-mechanical polishing process of the layer is detected; and (4) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface. The polishing agent may be a slurry having predetermined chemical characteristics.
In yet another aspect, the present invention provides a chemical-mechanical polishing apparatus for removing at least portions of a layer deposited on a surface of an integrated circuit substrate. The apparatus includes: (1) means for performing a first stage of polishing the substrate surface, the means for performing the first stage of polishing maintaining a predetermined difference between a rotational velocity of a polishing pad and a rotational velocity of a substrate holder allowing an endpoint of the chemical-m
Amberiadis Kostas
Kinoshita Osamu
Mizuno Hiroshi
Murohashi Tetsuaki
Sakuma Yoshifumi
LSI Logic Corporation
Lund Jeffrie R.
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