Abrading – Precision device or process - or with condition responsive... – With indicating
Reexamination Certificate
2000-10-26
2004-01-06
Eley, Timothy V. (Department: 3724)
Abrading
Precision device or process - or with condition responsive...
With indicating
C451S008000, C451S066000, C451S288000, C451S041000
Reexamination Certificate
active
06672941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate.
More particularly, this invention relates to methods and apparatus to planarize a semiconductor substrate having shallow trench isolation while reducing dishing and minimizing erosion of silicon nitride on the surface of the semiconductor substrate.
2. Description of Related Art
Chemical/mechanical planarization (CMP) of a semiconductor substrate is well known in the art. A description of CMP is found in
ULSI Technology
, Chang and Sze, McGraw-Hill Co. Inc., New York, N.Y., 1996, pp. 434-439 and is shown in FIG.
1
. The requirements for polishing a dielectric are the removal of material while maintaining uniformity across the entire semiconductor substrate. The CMP involves the use of chemistry as well as mechanical abrasion for the removal of material.
A polishing station
100
of CMP machine is equipped with a rotating platen
5
. A polishing pad
10
is attached to the platen
5
. A semiconductor substrate
20
is secured to the wafer carrier
15
. The wafer carrier
15
is lowered to place the semiconductor substrate
20
in contact with the polishing pad
10
. The wafer carrier
15
is rotated at a speed independent of the platen
5
and the wafer carrier
15
is adjusted to exert force on the platen
5
.
A polishing slurry
25
is delivered from the slurry supply
30
to ensure uniform wetting of the polishing pad
10
as well as proper delivery and recovery of the polishing slurry
25
. The polishing slurry
25
consists primarily of colloidal silica suspended in a solution of potassium hydroxide (KOH).
A CMP machine will have multiple polishing stations
100
connected by automated cassette-to-cassette handlers and automatic wafer loaders.
The basic polishing mechanism for polishing silicon dioxide (SiO
2
) dielectric is the same as for glass polishing. The mechanical removal rate is given by Preston's equation:
R=K
p
pv
where:
R is the rate of removal of material,
p is the applied pressure between the semiconductor substrate
20
and the platen
5
,
v is the relative velocity between the semiconductor substrate
20
and the platen
5
, and
K
p
is a constant of proportionality.
Preston's constant K
p
is a function of the mechanical properties of the silicon dioxide dielectric such as hardness and Young's modulus, the polishing slurry, and the structure of the polishing pad.
The above equation is a mechanical description of the rate of removal of material during planarization. However, the microscopic action of polishing is both chemical and mechanical. The exact mechanism of polishing is currently not well understood, but the present description of polishing divides the chemical process into four stages. In the first stage, hydrogen bonds with the oxide surfaces of the semiconductor substrate
20
. The second step has the hydrogen bonds of the slurry
25
and semiconductor substrate
20
joining together. In the third step, the silicon of the slurry
25
and the semiconductor substrate
20
are bonded to a common oxygen atom to form a molecular bond. The fourth step has the slurry
25
moving away transporting the molecular silicon with it, thus removing material from the surface of the semiconductor substrate
20
.
The above described stages have three important implications: Polishing is not just abrasion of the silica of the slurry
25
against the semiconductor substrate
20
. The presence of water and the PH of the solution affect the formation of hydrogen bonds. Further, the size and composition of the particles of the slurry
25
determine the effectiveness. The most common particulate used in the slurry
25
is silica with a particle size of 10 nanometers to 90 nanometers.
It is apparent from Preston's equation that the rate of removal R is directly related to the applied pressure p and the velocity v of platen. The rate of removal of material as shown in FIG.
4
and the selectivity of the chemical/mechanical planarization polishing as shown in
FIG. 5
are generally plotted versus the product of platen pressure and platen speed.
Refer now to
FIGS. 2
a
and
2
b
for a discussion of the problems associated with the current CMP practice of prior art for polishing a semiconductor substrate having shallow trench isolation (STI). A semiconductor substrate
200
has a layer of silicon dioxide SiO
2
210
formed on the top surface. On the layer of SiO
2
layer
210
, a layer of Silicon Nitride Si
x
N
y
is deposited to form a planarization stop layer
215
.
A photolithographic mask (not shown) is formed on the planarization stop layer
215
. The photolithographic mask is exposed to create a pattern for the shallow trenches
205
a
,
205
b
,
205
c
, and
205
d
that are to be created on the surface of the semiconductor substrate
200
. The areas that are to be the shallow trenches
205
a
,
205
b
,
205
c
, and
205
d
are removed from the photolithographic mask. The surface of the semiconductor substrate
200
is exposed to an etchant to remove the planarization stop layer
215
, the SiO
2
layer
210
, and a portion of the semiconductor substrate
200
to thus form the shallow trenches
205
a
,
205
b
,
205
c
, and
205
d
. A SiO
2
fill
220
is deposited on the surface of the semiconductor substrate
200
. The deposition of the SiO
2
fill is generally accomplished by a chemical vapor deposition of ozone—Tetraethylorthosilane (O
3
-TEOS) or by a Spin-On-Glass (SOG) process that is well known in the art. The SiO
2
fill
220
is then removed by a CMP process as described above.
The SiO
2
fill
220
is intended to be removed until the surface is level with the planarization stop layer
215
. However, the CMP process of the prior art causes three types of problems at the surface of the semiconductor substrate
200
. The first problem is shown in
FIG. 2
b
section
1
. The surface of the semiconductor substrate
200
is over polished causing erosion and thus a thinning of the Si
x
N
y
planarization stop layer
215
.
The second problem is illustrated in
FIG. 2
b
section
11
. The surface of the semiconductor substrate
200
is again over polished, however in this instance irregularities in the platen causes over polishing which causes dishing. The dishing is caused in areas of large shallow trenches
205
c
, and
205
d
and entirely removes the planarization stop layer
207
.
The third problem is shown in
FIG. 2
b
section III. Areas of the surface of the semiconductor substrate
200
are under polished. This leaves areas of SiO
2
fill
220
on the surface of the planarization stop layer
215
.
U.S. Pat. No. 5,575,706 (Tsai et al.), assigned to the same assignee as this invention, discloses an improved and new apparatus and process for chemical mechanical planarization (CMP) of a semiconductor wafer surface. The polish removal rate is controlled through the application of an electric field between the semiconductor wafer carrier and the polishing pad. Further, application of an electric field between selected regions of the semiconductor wafer carrier and polishing pad affects the polish removal rates in a manner which improves the uniformity of material removal across the entire semiconductor wafer surface. The uniformity of polish removal rate is further controlled through the application of bi-directional electric fields between the semiconductor wafer carrier and the polishing pad.
The novel features of the polishing apparatus of Tsai et al. is applying an electric field between the wafer carrier and polishing platen as a means of controlling the concentration of the polishing slurry across the surface of the semiconductor wafer being polished. The control of the concentration of the slurry and thus of the polish removal rate will improve the uniformity of polish removal rate across the semiconductor wafer surface.
U.S. Pat. No. 4,671,851 (Beyer et al) discloses a method for removing the aspirates, typically the ridge-shaped SiO
2
protuberances (so-
Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Eley Timothy V.
Knowles Billy
Saile George O.
Taiwan Semiconductor Manufacturing Company
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