Static information storage and retrieval – Read/write circuit – Testing
Patent
1993-06-11
1996-01-09
Beausoliel, Jr., Robert W.
Static information storage and retrieval
Read/write circuit
Testing
G11C 2900
Patent
active
054834929
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of checking the post-erasure contents of an erasable permanent memory, especially of EPROM type.
It also concerns a device for its implementation as well as a memory incorporating this device.
2. Discussion of the Related Art
Rational use of erasable permanent memories, especially of EPROM type, involves systematic checking of the contents of these memories after every erasure operation.
Now, hitherto, the checking of the contents of a memory after erasure was performed by writing an instruction into an instruction register of the memory, having the effect of storing the value of an address and of reading the contents at this address after a necessary recovery time which, by way of example, may be of the order of 6 .mu.s.
This operation of writing an instruction and of reading must be performed for each address to be checked, this entailing significant loss of time in an industrial context. Furthermore, such checking is performed several times while the memory has not been acknowledged to be completely erased, which may lead to a total checking time greater than a second.
SUMMARY OF THE INVENTION
An aim of the invention is to remedy these disadvantages by providing a method of checking the post-erasure contents of an erasable permanent memory endowed with an instruction register and with an address register, comprising a first step of writing an erasure-checking instruction word into this instruction register, followed by a second step of timing-out of predetermined duration.
According to the invention, the first step of writing the instruction word initiates the following sequence: incrementation of this address until the entire memory has been checked, and
Thus, with the method according to the invention, the entire checking includes just a single write operation and therefore requires just a single recovery time-out. With the address register of the memory being kept open throughout the duration of the checking, the internal address bus of the memory is then in direct communication with the bus of the digital system within which the relevant memory is situated and the reading of the memory plane may be performed at a frequency which is not limited by the recovery time related to the implementation of a write cycle.
According to a preferred form of the invention, the loop comprises a step of reading the memory datum held in the current address, followed by a step of comparison of said datum with a reference erasure datum, said step of comparison leading either to a new iteration in the case of identity, or to the execution of a new erasure sequence in the case of non-identity.
According to another aspect of the invention, the device for checking the post-erasure contents of an erasable permanent memory, especially of EPROM type, said memory comprising an address register, an instruction register connected to an internal databus via a status decoder, and an edge detector receiving as input a write enable signal, implementing the above method, is such that it furthermore comprises means for generating an address-transfer enable signal applied to the address register on the basis of a fast erasure-checking signal generated by the instruction register and of an address clock signal generated by the edge detector.
Moreover, the aforesaid device may be incorporated with EPROM memories with various structures.
Other features of the invention will emerge further from the description below.
BRIEF DESCRIPTION OF THE DRAWINGS
In the attached drawings given by way of nonlimiting examples:
FIG. 1 is a flow diagram explaining the essential steps of an erasure algorithm implementing the method according to the invention;
FIG. 2 is a simplified functional diagram of an embodiment of the device according to the invention;
FIG. 3 is a timing diagram illustrating the sequential running of the method of checking according to the invention.
FIG. 4 is a block diagram of the EPROM and the digital system that executes the eras
REFERENCES:
patent: 3727039 (1973-04-01), Baker et al.
patent: 4430735 (1984-02-01), Catiller
patent: 4680762 (1987-07-01), Hardee et al.
patent: 4905191 (1990-02-01), Arai
patent: 4926424 (1990-05-01), Maeno
patent: 4942576 (1990-07-01), Busach et al.
patent: 4972372 (1990-11-01), Ueno
patent: 5023874 (1991-06-01), Houston
patent: 5062109 (1991-10-01), Ohshima et al.
patent: 5325367 (1994-06-01), Dekker et al.
Nakayama et al "A 60 ns 16-Mb Flash EEPROM with Program and Erase Sequence Controller" IEEE Journal of Solid State Circuits vol. 26, No. 11, Nov. 1991.
Beausoliel, Jr. Robert W.
Driscoll David M.
Morris James H.
Palys Joseph E.
SGS-Thomson Microelectronics S.A.
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