Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-03-31
2002-07-16
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S063000, C365S207000
Reexamination Certificate
active
06421289
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit design. In particular, the present invention relates to charge-transfer pre sensing in memory devices.
BACKGROUND OF THE INVENTION
As memory devices get smaller, the silicon oxide thickness of devices is reduced. The oxide thickness is directly related to the breakdown voltage of the device. The breakdown voltage is the maximum voltage that may be applied to the device before it breaks down. However, as memory devices get smaller, the threshold voltage and trip voltages are not scaled in similar proportion to the breakdown voltage. The threshold voltage is the minimum voltage required to turn-on the memory device. The trip voltage is the voltage at which an inverter “flips.” A properly balanced inverter will trip at half its supply voltage level.
The number of transistors integrated on integrated circuits continue to increase as the size of devices are scaled down. As device sizes are decreased, the supply voltage as well as threshold voltage needs to be scaled to provide higher performance. The impact of inter-transistor variations on integrated circuits in terms of performance becomes more significant. One variation is the threshold voltage variation.
There exists a fundamental variability in the threshold voltage Vt due to the finite number of dopant atoms in the extremely small MOSFET channel area. This is true even in the absence of systematic variations, such as, implant nonuniformities, and Leff and Weff variations. Threshold variations will impact the design of high performance CMOS circuits. It causes the integrated logic circuit to be unstable or return uncertain results. A larger voltage margin must be used to warrant correct device operation without sacrificing performance.
In a dynamic RAM circuit, voltage differences are created during the read phase of the operation from charge sharing. Charge transfer is a scheme used to amplify the voltage difference created by reading the storage device using a single transistor.
FIG. 1
is a block diagram of a prior art charge-transfer pre-sensing scheme with Vcc/2 bit line pre-charging. Bit line (BIT)
101
is connected with bit line capacitor
111
and transfer gate (M
TG
1
)
120
. Sense amplifier capacitor
131
is connected to transfer gate
120
and sense amplifier
140
. Bit bar line (BIT)
151
is connected with bit bar line capacitor
161
and transfer gate (M
TG
2
)
170
. Sense amplifier capacitor
181
is connected to transfer gate
170
and sense amplifier
140
. Sense amplifier
140
is a cross-coupled amplifier including first inverter
141
and second inverter
142
connected between sense amplifier capacitor
131
and sense amplifier capacitor
181
.
First inverter
141
, second inverter
142
, transfer gate (M
TG
1
)
120
, and transfer gate (M
TG
2
)
170
suffer from variations in their associated threshold voltages. For example, even though they are all transfer gates, the threshold voltages of M
TG
1
120
and M
TG
2
170
are not necessarily the same, nor are the threshold voltages of inverters
141
and
142
necessarily the same.
A DC power supply voltage (Vcc) is applied to the memory device
100
. Initially both Bit and Bit bar line voltages V
B
110
and V
B
160
are pre-charged to Vcc/2, therefore, pre-charging C
BIT
111
and
161
. Then the transfer gate
149
is turned off and, either V
B
110
or V
B
160
is brought to a new voltage either lower or higher than Vcc/2 depending on what content is stored. At the same time, Bit line
110
sense amplifier voltage (V
SA
)
130
and Bit bar line
160
sense amplifier voltage (V
SA
)
180
are pre-charged to Vcc; therefore, pre-charging sense amplifier capacitors (C
SA
)
131
,
181
.
C
SA
131
,
138
are chosen to have a capacitance of a fraction of C
BIT
111
,
161
. Thus, when the transfer gate
149
is turned on, charge transfers from C
SA
131
,
181
to C
BIT
111
,
161
and a large voltage change develops at V
SA
130
and V
SA
180
. The large voltage change is sensed by sense amplifier
140
.
Design problems occur when the device fails to turn on, because voltages can not be applied that are high enough to overcome the required threshold voltage without exceeding the breakdown voltage of the device. This makes the reliable sensing of voltage differences developed between Bit line
101
and Bit bar line
151
, increasingly difficult.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for charge-transfer pre-sensing in memory devices. The apparatus splits a first data line into two or more segments. Each segment is connected to one or more transfer gate and sense amplifier. A second data line is split into two or more segments. Each segment is connected to one or more transfer gate and sense amplifier. A voltage differential is provided between each of the sense amplifiers. At least one of the voltage differences is an incorrect voltage difference that is corrected by the other voltage differences.
REFERENCES:
patent: 5226005 (1993-07-01), Lee et al.
patent: 5796671 (1998-08-01), Wahlstrom
Lu Shih-Lien
Somasekhar Dinesh
Blakley Sokoloff Taylor & Zafman LLP
Intel Corporation
Lebentritt Michael S.
Nguyen Van Thu
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