Method and apparatus for characterizing arrays using...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Reexamination Certificate

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07398495

ABSTRACT:
The present invention provides a method and apparatus for characterizing a memory array. The method includes accessing information indicative of a transistor-level circuit design of a column of a memory array and determining at least one component of a cell representative of the column of the memory array based on the information indicative of the transistor-level circuit design and at least one timing rule for at least one signal associated with the column of the memory array. The method also includes determining at least one time delay associated with the cell based on the at least one component of at least one cell.

REFERENCES:
patent: 7031898 (2006-04-01), Jain et al.
patent: 7315992 (2008-01-01), Bhooshan et al.
patent: 2003/0009318 (2003-01-01), Amatangelo et al.

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