Method and apparatus for characterizing arrays using...

Details Method and apparatus for characterizing arrays using... Method and apparatus for characterizing arrays using...

2008-07-08

2008-07-08

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07398495

ABSTRACT:
The present invention provides a method and apparatus for characterizing a memory array. The method includes accessing information indicative of a transistor-level circuit design of a column of a memory array and determining at least one component of a cell representative of the column of the memory array based on the information indicative of the transistor-level circuit design and at least one timing rule for at least one signal associated with the column of the memory array. The method also includes determining at least one time delay associated with the cell based on the at least one component of at least one cell.

REFERENCES:
patent: 7031898 (2006-04-01), Jain et al.
patent: 7315992 (2008-01-01), Bhooshan et al.
patent: 2003/0009318 (2003-01-01), Amatangelo et al.

Affiliated with

Also associated with

Rating

Method and apparatus for characterizing arrays using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for characterizing arrays using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for characterizing arrays using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2811369