Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
1999-08-10
2001-11-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C439S620180, C029S025010
Reexamination Certificate
active
06319737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor device design and fabrication and, more particularly, to a method and apparatus for analyzing characterization data for a semiconductor device.
2. Description of the Related Art
The requirements for high density performance associated with ultra large scale integration semiconductor devices continue to escalate, hence requiring design features of 0.25 microns and under (e.g., 0.18 microns and under), increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for competitiveness. For example, memory devices are one class of semiconductor devices that require high-density performance and ultra large-scale integration. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor manufacturing techniques. Moreover, as design features are reduced into the deep submicron range, it becomes increasingly difficult to maintain or improve manufacturing throughput for competitiveness.
Market forces continue to demand higher capability and faster circuits. In order to satisfy market demands, the size of individual chips is increased to accommodate more transistors. A reduction in the size of the individual transistors also accounts for a greater number of transistors on each chip. Furthermore, in order to maintain satisfactory productivity and yield, it is necessary to process larger wafers, often at much higher costs, and utilize automatic handling equipment in order to maintain uniformity across larger wafers and between different wafers.
The Ultra Large Scale Integration (ULSI) era has significantly increased the number of process steps associated with the fabrication of wafers. The number of tests necessary to maintain product quality has also increased drastically. Consequently, it has become progressively more difficult to generate characterization data for complex semiconductor devices. The characterization data corresponds to product attributes and variables data collected from assembled units from die on wafers that have been processed either to standard or specific modifications of the associated fabrication process. For example, the characterization data includes: information that indicates the process versus product yield; distribution of results from various tests performed on the fabricated devices, such as transition time for switching between a high state and a low state; percentage of devices that generate unsatisfactory results for specific tests; performance of fabricated devices relative to design requirements; etc.
Accurate characterization of product performance and circuit parameters is crucial for providing product stability. For example, the product characterization data can summarize test results on the same device type to compare the product performance results to the wafer electrical tests (WET) of the fabrication process. Based on the test results, an engineer can determine which WET characteristics effect the product performance and/or yield either in a positive or negative way. The engineer may then relate this information to the product design and fabrication engineers to determine if the product needs to be re-designed to meet the fabrication process area or the process can be retargeted for the best product performance and yield. In addition, proper characterization ensures that a particular device displays appropriate performance characteristics and conforms to customer specifications.
Traditional approaches to generating characterization data require that numerous wafer electrical tests (WET) be conducted on selected semiconductor devices that are formed on the wafer during the fabrication process. The WET data collected represents various electrical parameters (e.g., electrical conductivity, resistance, and transition time from a low to high state, etc.) that the product designers must consider when using the associated engineering design rules (EDR) in the design of a semiconductor device. As the number of fabrication steps has increased, so too has the number of tests that must be performed on the wafer in order to accurately monitor fabrication of the semiconductor device.
In order to generate characterization data that accurately represents the product design, packaged units must be assembled from wafers that exhibit those WET characteristics that most closely match the EDR requirements. Analysis of the data provides the engineer with information to verify the product design and how the product performance relates to the fabrication process area.
Accordingly, one problem associated with current methods of generating characterization data for semiconductor devices, is the amount of time required to thoroughly analyze the collected variables data. Another problem associated with current methods of generating characterization data is the inconsistency associated with the data analysis when multiple engineers must analyze different portions of the data.
DISCLOSURE OF THE INVENTION
There is a need for an arrangement for quickly analyzing data collected from a semiconductor device characterization and generating consistent result summaries that can be used to quickly identify product performance and yield issues. These result summaries can also be used to communicate the product performance and/or yield issues to the design and fabrication engineers.
These and other needs are addressed by the present invention, wherein characterization data for a semiconductor device is quickly and consistently analyzed by comparing the measured test results from fabricated semiconductor devices to specific performance limit criteria based on the design simulation and customer requirements included in the product test program.
In accordance with one aspect of the invention, a method is provided for generating product characterization reports for a semiconductor device. The method comprises the steps: compiling a WET data set containing measured results from WET tests performed on wafers from characterization lots formed from a prescribed fabrication process; generating WET reports from the WET data set for determining a group of wafers most suitable to be assembled for characterization tests; compiling a characterization data set containing measured results from characterization tests performed on the assembled semiconductor units; analyzing the characterization data set to identify those characterization test parameters that fail the performance requirements; determining whether the characterization data set needs modification based on the analyzing of the characterization data set; and generating product characterization reports for the semiconductor device based on the valid data set. The present method allows generation of product characterization reports for complex semiconductor devices in a fraction of the time traditionally required by quickly examining the data collected from the fabrication process and the characterization tests. Additionally, the characterization reports are accurately and consistently generated because prescribed statistical analyses are used instead of human intuition from multiple engineers.
Hence, an engineer may easily review WET data to accurately select wafers that meet engineering design rules. Package units can then be assembled from the selected wafers for product variables data collection. The characterization data set enables quick identification of any semiconductor devices that do not meet prescribed performance limits based on the measured characterization test parameters.
Additional advantages and novel features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5719495 (1998-02-01), Mosle
Cheng Jennifer Meng-Tzu
Putnam Gary Gene
Sun Chin-Yang
Advanced Micro Devices , Inc.
Niebling John F.
Stevenson Andre′
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