Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-15
2008-04-15
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07360188
ABSTRACT:
A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a user defined delta value. If the compared areas differ greater than the user defined delta value, then a coordinate change is computed for moving the signal wire to reduce characteristic impedance discontinuity.
REFERENCES:
patent: 6532439 (2001-10-01), Anderson et al.
patent: 6845492 (2005-01-01), Frank et al.
patent: 2005/0246669 (2005-11-01), Yamazaki
Garbowski Leigh M.
International Business Machines - Corporation
Pennington Joan
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