Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1999-12-21
2003-08-26
Gaffin, Jeffrey (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S300000, C713S323000
Reexamination Certificate
active
06611918
ABSTRACT:
BACKGROUND
The present application teaches a circuit for use in reducing power consumption of a real time clock in a computer system.
When a personal computer is turned off, an on-board battery, e.g. a 3-volt lithium battery, may still power certain circuits in the computer. For example, a real time clock often still maintains the time using battery power when the primary computer power supply goes offline.
The smaller transistors that are now used to make such circuits in order to fit more transistors on a substrate, often have higher leakage currents. These transistors consume undesired current when they are biased to the “off” state. This increases the DC load that is placed on the battery, when the computer power supply is off due to off state current, which can cause the battery to deplete more quickly.
SUMMARY
The present disclosure defines a device which reduces power consumption during battery powered operation of the Real Time Clock.
The application discloses a leakage reduction device for a real time clock system, that has a real time clock circuit, having separated first and second power supply connections, and maintaining a count indicative of real time; and an associated circuit, which operates in a first mode when a power supply voltage is present and operates in a second mode when battery power is present, said second mode providing a biasing condition that minimizes off state leakage current during battery operation.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects will be described in detail with reference to the accompanying drawings, wherein:
FIG. 1
shows a schematic diagram of the circuitry including the real time clock well.
FIG. 2
shows a block diagram of a power monitoring embodiment.
REFERENCES:
patent: 5838171 (1998-11-01), Davis
patent: 5909140 (1999-06-01), Choi
patent: 5917365 (1999-06-01), Houston
patent: 6191470 (2001-02-01), Forbes et al.
patent: 6307233 (2001-10-01), Awaka et al.
patent: 6373321 (2002-04-01), Yamauchi et al.
patent: 6380798 (2002-04-01), Mizuno et al.
patent: 10189884 (1998-07-01), None
Muhammad M. Khellah and M.I.Emasry, Power Minimization of High-Performance Submicron CMOS Circuits Using a Dual-Vd Dual-Vth (DVDV) Approach, Proceedings 1999 international symposium on Low power electronics and design Aug. 1999, ACM, pp. 106-108.*
Roy, K.; “Leakage power reduction in low-voltage CMOS designs”, Electronics, Circuits and Systems, 1998 IEEE International Conference on , vol.: 2 , 1998, pp. 167 -173 vol. 2.*
Anonymous,Diode Battery Back-Up Switch, IBM Technical Disclosure Bulletin, vol. 30, No. 2, Jul. 1, 1987 p. 895.
Fish & Richardson P.C.
Gaffin Jeffrey
Trujillo James K.
LandOfFree
Method and apparatus for changing bias levels to reduce CMOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for changing bias levels to reduce CMOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for changing bias levels to reduce CMOS... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3090271