Method and apparatus for cascade programming a chain of...

Details Method and apparatus for cascade programming a chain of... Method and apparatus for cascade programming a chain of...

2005-11-01

2005-11-01

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C716S030000, C716S030000, C365S185290, C365S218000

Reexamination Certificate

active

06960935

ABSTRACT:
A system for clearing and programming the memory of an FPGA IC, when the IC is comprised of a plurality of cores. The system clears the memory of the of cores. The system then sequentially verifies completion of clearing memory of each core. The system then provides a programming ready signal to all cores when the memory of a last core has has been cleared. The system then sends the bitstream data to a first core. After the first core is programmed, the balance of the bitstream data is sent to a next core. This process is repeated until all of the cores are programmed.

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“VariCore™ Embedded Programmable Gate Array Core (EPGA™) 0.18 μm Family” Release 2.0, Actel Corporation, pp. 1-16, Jun. 2001.

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