Method and apparatus for calibrating a read/write channel in...

Details Method and apparatus for calibrating a read/write channel in... Method and apparatus for calibrating a read/write channel in...

2011-05-03

2011-05-03

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S210100, C365S189150, C365S206000

Reexamination Certificate

active

07936630

ABSTRACT:
Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing data into and reading data from the memory cells. At least two memory cells are employed as reference cells to output a plurality of pilot signals. The memory apparatus also includes a channel block operatively coupled to the memory block, and adapted to facilitate the writing and reading of data into and from the memory cells. The channel block is also adapted to receive the pilot signals and determine one or more disturbance parameters based at least in part on the pilot signals and to compensate the read back signals based at least in part on the determined one or more disturbance parameters during said reading of data from the memory cells. Other embodiments may be described and claimed.

REFERENCES:
patent: 5926413 (1999-07-01), Yamada et al.
patent: 6385111 (2002-05-01), Tran et al.
patent: 6504778 (2003-01-01), Uekubo
patent: 6590804 (2003-07-01), Perner
patent: 6791880 (2004-09-01), Kurihara et al.
patent: 7649793 (2010-01-01), Ramamoorthy et al.
patent: 2001/0053104 (2001-12-01), Tran et al.

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