Method and apparatus for calculating wiring capacitance, and...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07861194

ABSTRACT:
A diagonal-capacitance calculating unit calculates diagonal capacitance based on the adjacent wirings in diagonally upward and downward direction from a target wiring. A basic-capacitance correcting unit corrects basic capacitance, which is wiring capacitance based on adjacent wirings in above, below, on a left of, and on a right of the target wiring, based on the adjacent wirings in diagonally upward and downward direction from the target wiring. A total-capacitance calculating unit adds up the diagonal capacitance calculated and the basic capacitance corrected, to calculate wiring capacitance of the target wiring.

REFERENCES:
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patent: 6574782 (2003-06-01), Dewey et al.
patent: 2004/0049751 (2004-03-01), Teig et al.
patent: 2004/0088664 (2004-05-01), Srinivasan
patent: 2004/0103384 (2004-05-01), Tanaka
patent: 2004/0216067 (2004-10-01), Tanaka et al.
patent: 2005/0097494 (2005-05-01), Kitahara et al.
patent: 2005/0183049 (2005-08-01), Ohba et al.
patent: 2005/0193354 (2005-09-01), Ohba et al.
patent: 2001-230323 (2001-08-01), None
patent: 2002-299456 (2002-10-01), None
patent: 2004-38395 (2004-02-01), None
Peter Habitz et al., “IBM ASICs Redefine Performance Standard for Parasitic Extraction”,IBM Microelectronics, vol. 7, No. 4, Fourth Quarter 2001.
Communication mailed from the Japanese Patent Office on Nov. 10, 2009 in the corresponding Japanese patent application No. 2004-254576.
Concise explanation of references AG (JP 2002-299456) and AH (JP 2004-38395) cited herein.

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