Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Patent
1997-01-06
1999-01-12
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
395393, G06F 1200
Patent
active
058601546
ABSTRACT:
A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.
REFERENCES:
patent: 5408626 (1995-04-01), Dixit
Popescu, et al., "The Metaflow Architecture," IEEE Micro, pp. 10-13 and 63-73, Jun. 1991.
Superscalar Microprocessor Design, Mike Johnson, Prentice-Hall, Englewood Cliffs, NJ, chap 3, 1991.
Abramson Jeffrey M.
Akkary Haitham
Glew Andrew F.
Hinton Glenn J.
Konigsfeld Kris G.
Intel Corporation
Lane Jack A.
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