Method and apparatus for cache space allocation

Details Method and apparatus for cache space allocation Method and apparatus for cache space allocation

2005-03-29

2005-03-29

Lane, Jack A. (Department: 2188)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S128000, C711S145000, C711S163000, C711S209000

Reexamination Certificate

active

06874057

ABSTRACT:
A method and apparatus are disclosed for allocating a section of a cache memory to one or more tasks. A set index value that identifies a corresponding set in the cache memory is transformed to a mapped set index value that constrains a given task to the corresponding allocated section of the cache. The allocated cache section of the cache can be varied by selecting an appropriate map function. When the map function is embodied as a logical and function, for example, individual sets can be included in an allocated section, for example, by setting a corresponding bit value to binary value of one. A cache addressing scheme is also disclosed that permits a desired portion of a cache to be selectively allocated to one or more tasks. A desired location and size of the allocated section of sets of the cache memory may be specified.

REFERENCES:
Kaxiras et al, “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power,” IEEE, (2001).
Lai et al., “Dead-Block Prediction & Dead-Block Correlating Prefetchers,” IEEE, (2001).
Mendelson et al, “Modeling Live and Dead Lines in Cache Memory System,” IEEE, Trans. on Computers, v. 42, No. 1, (Jan. 1993).

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