Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-03-24
1998-09-15
Sheikh, Ayaz R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711133, 711144, 711159, 711168, G06F 1212
Patent
active
058095241
ABSTRACT:
A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.
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Bauer John M.
Rhodehamel Michael W.
Sarangdhar Nitin V.
Singh Gurbir
Wang Wen-Hann
Etienne Ario
Intel Corporation
Sheikh Ayaz R.
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