Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-01-27
2002-05-21
Robertson, David L. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06393522
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates generally to computer systems and, more specifically, to techniques for managing cache memory.
BACKGROUND OF THE INVENTION
In a typical computer system, a processor receives data to be processed from a main memory. After the processing is complete, the processor stores results in the main memory. However, a processor often operates at a faster rate than the rate at which the main memory can provide data and store results. Thus, the main memory imposes a limitation on the performance of the processor. To avoid this limitation, a faster type of memory, referred to as a cache, is interposed between the processor and the main memory. The cache is used to store frequently used data so that the frequently used data may be provided to the processor more quickly, thereby reducing the average time needed to provide data from the main memory to the processor.
As computer systems have increased in complexity, processors have been provided with multiple caches. However, with multiple caches, a decision must be made as to which cache will be used to process a particular element of data or a result. In the past, the assignment of data to a cache has been essentially random. While random assignment of data among multiple caches is feasible for some applications, it does not provide the most efficient use of the multiple caches. Thus, a technique is needed to improve the performance of a computer system having multiple caches.
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ATI International SRL
Robertson David L.
Vedder Price Kaufman & Kammholz
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