Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Patent
1997-11-26
2000-10-17
Cabeca, John W.
Electrical computers and digital processing systems: memory
Address formation
Generating prefetch, look-ahead, jump, or predictive address
711204, 711137, 712237, 712239, G06F 1208
Patent
active
061346438
ABSTRACT:
A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The prediction table cache is adapted to store a plurality of entries defining an access history of previously encountered memory requests. The prediction table cache is indexed by the identifier. The prefetch controller is adapted to receive the memory request and generate at least one prefetch candidate based on the memory request and the access history. A method for prefetching data in a microprocessor includes receiving a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The memory request is compared to an access history of previously encountered memory requests. The access history is indexed by the identifier. At least one prefetch candidate is generated based on the memory request and the access history.
REFERENCES:
patent: 4807110 (1989-02-01), Pomerene et al.
patent: 5093777 (1992-03-01), Ryan
patent: 5146578 (1992-09-01), Zangenehpour
patent: 5148538 (1992-09-01), Celtruda et al.
patent: 5287487 (1994-02-01), Priem
patent: 5293609 (1994-03-01), Shih et al.
patent: 5305389 (1994-04-01), Palmer
patent: 5317718 (1994-05-01), Jouppi
patent: 5345560 (1994-09-01), Miura et al.
patent: 5694568 (1997-12-01), Harrison, III et al.
patent: 5761706 (1998-06-01), Kessler et al.
patent: 5778436 (1998-07-01), Kedem et al.
patent: 5822790 (1998-10-01), Mehrotra
Chen et al, "A Performance Study of Software and Hardware Data Prefetching Scheme", 1063-6897/94 IEEE pp. 223-232 (Apr. 1994).
Jouppi, Norman P., "Improving Direct-Mapped Capped Performance by the Addition of a Small Fully-Associate Cache and Prefetch Buffers", CH2887-8/90/000/0364 IEEE pp. 364-373(May 1990).
Krishnan et al., "Optimal Prediction for Prefetching in the Worst Case", DUKE-CS-93-26 pp. 1-24 (Date: unknown).
Joseph et al., "Prefetching Using Markov Predictors", ACM 0-89791-901-7/97/0006 pp. 252-263 (1997).
Lopriore, Lanfranco, "Line Fetch/Prefetch in a Stack Cache Memory", 0141-9331/93/090547-09 Butterworth-Heinemann Ltd., Microprocessors and Microsystems vol. 17, No. 9 (Nov. 1993).
Palmer et al., "Fido: A Cache That Learns to Fetch", Proceedings of the 17th International Conference on Very Large Data Bases pp. 255-264 (Sep. 1991).
Eickemeyer et al., "A Load-Instruction Unit For Pipelined Processor", IBM J. Res. Develop., vol. 37, No. 4 pp. 547-564 (Jul. 1993).
Vitter et al., "Optimal Prefetching via Data Compression", Brown-CS-91-46, pp. 1-19 (Date: unknown).
Alexander et al., "Distributed Prefetch-Buffer/Cache Design for High Performance", 0-8186-7237-4/96 IEEE pp. 254-263 (1996).
Pinter, Shlomit S. and Yoaz, Adi, "Tango: a Hardware-Based Data Prefetching Technique for Superscalar Processors" (Date: unknown).
Kedem Gershon
Ronen Ronny
Yoaz Adi
Cabeca John W.
Intel Corporation
Peugh Brian R.
LandOfFree
Method and apparatus for cache line prediction and prefetching u does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for cache line prediction and prefetching u, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for cache line prediction and prefetching u will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-479484