Method and apparatus for cache coherency in an interconnecting n

Details Method and apparatus for cache coherency in an interconnecting n Method and apparatus for cache coherency in an interconnecting n

1997-11-21

2000-10-24

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711142, 711143, 711144, 711145, 711146, G06F 1212

Patent

active

061382175

ABSTRACT:
In a data processing system where a plurality of nodes, each having a plurality of processors and cache memories associated with each of the processors, are connected via a bus, tag information is added to each data block stored in the cache memories. The tag information has state information which includes information (INTERNODE-SHARED) indicative of whether or not the data block is cached in another node. When a write-access is transmitted to the data block in the cache memory, if the state information added to the data block is INTERNODE-SHARED, invalidation of the data block is requested to the other node.

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