Patent
1995-10-30
1997-11-18
Ray, Gopal C.
395855, G06F 1328, G06F 1300
Patent
active
056896590
ABSTRACT:
A data processing system (10) having a bus controller (5) that uses a communication bus (22) which adapts to various system resources (7) and is capable of burst transfers. In one embodiment, the processor core (2) and system resources (7) supply control signals supplying required parameters of the next transfer. The bus controller is capable of transferring operands and/or instructions in incremental bursts from these system resources. Each transfer data burst has an associated unique access address where successive bytes of data are associated with sequential addresses and the burst increment equals the data port size. The burst capability is dependent on the ability of system resource (7) to burst data and can be inhibited with a transfer burst inhibit signal. The length of the desired data is controlled by a sizing signal from the core (2) or from cache and the increment size is supplied by the resource (7).
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Arnold Ronny L.
Galloway Frank C.
Menard David M.
Revilla Juan Guillermo
Tietjen Donald L.
Motorola Inc.
Ray Gopal C.
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