Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-12-01
2001-07-10
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06259637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the replacement of defective memory cells in a semiconductor memory, and, more particularly, to the replacement of defective memory cells using a built-in self-test mechanism.
2. Description of the Related Art
A semiconductor memory device typically includes an array of memory cells, and the array is normally divided into a number of sub-arrays. Memory cells in the array are selected for reading and writing by means of row and column address signals input to the semiconductor memory device. The row and column address signals are processed by address decoding circuitry to select row lines and column lines in the array to access the desired memory cell or memory cells. A common practice in semiconductor memory devices is to implement the decoding at more than one level. For example, a first level decoding may yield data from a plurality of memory cells in the array, while a second level of decoding will select one memory cell, or a subset of memory cells, from the plurality. Thus, an address input to a semiconductor memory device will commonly result in the selection of a plurality of memory cells in the array or sub-array of the memory device, at least at a first level of decoding. That is, a plurality of memory cells will typically be selected by, or respond to, any particular address.
When semiconductor devices are manufactured, defective memory cells may occur in the memory array or in a sub-array. To salvage the semiconductor memory device despite these defective memory cells, and thus to increase overall yield in the manufacturing process, redundancy is commonly implemented. Redundant memory elements are located throughout the memory array, and each sub-array in the memory array will typically have associated with it a plurality of redundant memory elements. When a defective memory cell is detected in a sub-array, redundant decoding circuitry associated with the redundant memory elements for that sub-array may be programmed to respond to the address of the defective memory cell. When the address of the defective memory cell is input to the sub-array, the redundant memory element will respond in place of the defective memory cell. Redundancy and various methods for its implementation are known to those of ordinary skill in the art.
Redundant memory elements generally comprise redundant rows and/or redundant columns. When a defective memory cell is located, the row (or column) on which it is located may be replaced with a redundant row (or column) by programming, or otherwise altering, the row and column decoding circuitry. If a row in the memory array or sub-array contains two or more defective memory cells (each being on a different column), a single redundant row will suffice to “repair” the multiple “bad bits.” If a row in the memory array contains a single defective memory cell, either a redundant row or a redundant column may be used to replace the row or column containing the defective memory cell. During testing of memory arrays, numerous defective memory cells may be encountered, and the replacement of defective cells using a limited number of redundant rows and columns becomes complex. Unless the defective cells can be replaced, the memory array will be unsuitable. Moreover, in certain circumstances, a memory cell may be evaluated as defective at one time, whereas during a subsequent task, that memory cell may be evaluated as non-defective. Hence, the process of detecting and replacing defective memory cells has become extremely complex, particularly in view of the ever-increasing numbers of memory cells in memory arrays.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, an integrated circuit device comprises a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row and each column having coupled to it a plurality of memory cells. The integrated circuit device further comprises a first redundant row of memory cells, a first redundant column of memory cells, and a test circuit coupled to the memory array and adapted to test the plurality of memory cells coupled to each of the plurality of rows. The integrated circuit device further comprises a control circuit coupled to the test circuit and adapted to receive test results from the test circuit, the control circuit adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first redundant row and first redundant column. A first register is coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit, and a second register is coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit. In addition, a second redundant row of memory and a third register may be provided. The control circuit is adapted to determine an assignment of the second redundant row, and the third register is adapted to receive the assignment of the second redundant row.
In another aspect of the present invention, a method is provided for replacing defective memory cells in a memory array. The method comprises testing a first row of memory cells in the memory array, detecting a first defective memory cell coupled to the first row, providing row information and column information associated with the first defective memory cell to a control circuit, determining an assignment of one of a redundant row and redundant column to replace the first row, and storing the assignment in a register coupled to the control circuit.
REFERENCES:
patent: 6067260 (2000-05-01), Ooishi et al.
patent: 6115828 (2000-09-01), Tsutsumi et al.
Tupuri Raghuram S.
Wood Timothy J.
Zuraski, Jr. Gerald D.
Advanced Micro Devices , Inc.
Phan Trong
Williams Morgan & Amerson P.C.
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