Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1999-08-16
2001-01-30
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C711S100000, C711S114000, C709S241000, C709S241000, C709S241000
Reexamination Certificate
active
06182161
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to input/output (I/O) subsystems, in particular memory subsystems such as a Redundant Array of Independent Disks (RAID) subsystem. In particular, the invention relates to methods for building software to handle various memory operations.
U.S. Pat. No. 5,860,003, incorporated herein by reference, shows a modular software control system for an I/O subsystem. A central group of software modules are made to be hardware-independent, with interface modules translating to and from the host hardware configuration and the I/O subsystem hardware configuration. I/O commands are executed using a series of specialized threads, with each thread performing a particular function. An appropriate group of threads are assembled for each I/O command, the group being a “net”.
High performance and bandwidth is accomplished by having the threads independent and able to operate concurrently. In a RAID system, for example, if each net operates on a particular span of data in the disk drives, other nets can operate on other spans in the same disk drives concurrently. Even for a particular span of data, only particular threads within a net that actually use the disk drives need to lock up that span for the duration of the thread operation.
The span lock capability improves throughput over prior art systems where an entire physical disk drive needs to be locked to a particular I/O command. In addition, within a span, an error recovery routine may be run and only need to lock up a particular portion of that span. Thus, the thread discovering the error, or other threads, could use other portions of the span concurrently with the error recovery, further improving the bandwidth.
A core command engine is provided which is generic and can be used with any I/O system hardware. This is accomplished using a generic command module which communicates with a media module to obtain a particular net for an I/O command. The media module knows the configuration, such as RAID 3 or RAID 5, of the I/O subsystem. The command module need not know this information, and is generic. Even the media module does not know the particular hardware used, which is in turn dealt with by separate hardware interface modules.
As users are provided more flexibility in configuration, the number of nets expands dramatically. Different program nets are required to handle I/O operations with varying parameters, such as different RAID levels, different numbers of disk drives in the array, etc. Such a proliferation of options dramatically increases the programming complexity.
SUMMARY OF THE INVENTION
The present invention provides an improved method and apparatus for providing I/O operations. In particular, a particular I/O operation is programmed as a net in a matrix format. Upon initialization of the I/O subsystem, an intermediate representation of the net in matrix format is created. Subsequently, upon a running of the net operation, a complete version of the net data structure is created.
The present invention in one embodiment essentially provides a compiler that generates an intermediate representation of a net, and an interpreter that reads that representation when it is time to build a net. The interpreter does all the final mapping. The separation into two blocks for creation of a net allows optimization of the execution speed of the interpreter part, while not being burdened with optimizing the compiler part. This modularization and the use of a matrix configuration simplifies the programming of a net for an I/O operation, and automates the generation of the final, complete net.
Typically, while the matrix format in which the net was programmed is designed with a particular RAID level in mind, the intermediate matrix representation of the net will not require any knowledge of RAID level, and the interpreter portion of the net builder software will not make any decisions based on the RAID level. The intermediate representation will include all parameters necessary to construct the desired net geometry for all the allowable array widths. The final, complete net structure will be built to accommodate the actual array width, with the proper number of independent disk access threads and the appropriate number and mapping of data buffers.
The present invention provides an array or matrix representation of threads used in a net. The columns of the matrix define common thread buffer usage, while the rows of a matrix define parallel thread execution.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5745778 (1998-04-01), Alfieri
patent: 5860003 (1999-01-01), Eidler et al.
patent: 5950006 (1999-09-01), Crater et al.
patent: 6105053 (2000-08-01), Kimmel et al.
Manbert Rush C.
Perry David D.
Lee Thomas C.
MTI Technology Corp.
Perveen Rehana
Townsend and Townsend / and Crew LLP
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