Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-05
2003-02-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C365S051000
Reexamination Certificate
active
06519756
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of hardware description languages, and, more specifically, to building of integrated circuits such as ASICs.
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2. Background Art
Designers of integrated chips, such as application specific integrated chips (“ASIC”), typically rely on a computer aided design (“CAD”) program using a hardware description language to assist in their design. Hardware description languages allow the designer to specify, in software, the logical operation of the chip they are designing. Typical hardware description languages include Verilog, Synopsys MCL, and VHDL.
Present design processes consist of several steps. First, the designer writes a software program describing the flow of signals in the chip and the logical operations performed on those signals. In Verilog, for example, such a program is written at the so-called “Register Transfer Level” (“RTL”). Once the designer has programmed the operation of the logic circuit, the program is simulated and, if acceptable, synthesized into a corresponding collection of standard cells. Standard cells are components, such as logic gates, latches, decoders, and various other components, that exist in a library accessible by a synthesis tool. The synthesis step is typically an automated process in which the synthesis tool determines the appropriate standard cells and interconnections between standard cells to realize a circuit that satisfies the RTL model. At this point, the chip is ready for physical design; that is, the physical placement of the synthesized standard cells and the routing of interconnections (wires) among them. Physical designers typically use automated tools to aid in placement and routing.
Currently, the logical design (i.e., preparation of the RTL program) and the eventual physical design of the chip are separate steps in the design process. In fact, the two steps are often performed by separate people using separate tools, or the physical design may even be performed by a physical designer at another company. This decoupling of the logical and physical design has become unsatisfactory. For example, since the physical design is performed by a separate person, that person is likely not familiar with the overall function or desired performance of the chip as envisioned by the logic designer, which may lead to an inoperable physical design. As technology has advanced, the time delay introduced by physical components (“gate delay”) had decreased such that the delay introduced by interconnecting wires (“wire delay”) is of increasing importance. A physical layout that does not adequately account for wire delay could lead to a layout with unexpected delays in signal propagation which, as a result, does not meet the timing goals envisioned by the logic designer. As another example, a design may have a regularity to its structure that is not readily discoverable by the physical designer or by automatic placement algorithms. This regularity, known to the logic designer, is lost in the final physical design.
Circuit design is often an iterative process in which the same RTL description may be processed (i.e., synthesized and/or physically placed and routed) multiple times. The changes to the RTL description that cause the circuit to be reprocessed are often incremental changes to only a few modules within the circuit design. Other modules that are not dependent on the changed modules may be reprocessed unnecessarily, resulting in inefficient use of time and processing resources.
SUMMARY OF THE INVENTION
A method and apparatus for building an integrated circuit are described. A description of the logical operation of a module in a hardware description language is provided, which includes annotations in the form of design directives. An interpreting process is configured to red the annotations and identify which logical and physical design tools are needed to process each module in the description, as well as the order in which to invoke the logical and physical design tools.
In one or more embodiments, dependencies in the execution of the design tools on the various modules of the description are analyzed to determine whether the processing of modules may be performed in parallel to optimize execution. The dependency analysis comprises, for example, the generation of a dependency graph.
In one or more embodiments, the description and the intermediate results of the execution of the design tools are cached in memory. A current description is compared with a prior cached description to determine which modules are revised in the current description. Those execution steps that entail redundant processing of unrevised modules are bypassed, and the corresponding prior cached results are utilized in those instances.
REFERENCES:
patent: 5029102 (1991-07-01), Drumm et al.
patent: 5650955 (1997-07-01), Puar et al.
patent: 5764534 (1998-06-01), Goetting
patent: 6098068 (2000-08-01), Brown
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6345379 (2002-02-01), Khouja et al.
patent: 6356497 (2002-03-01), Puar et al.
patent: WO 95/32476 (1995-11-01), None
patent: WO 98/49638 (1998-11-01), None
James Hwang, Cameron Patterson, Eric Dellinger, Sujoy Mitra and Ralph Witting, “Generating Layouts for Self-implementing Modules”, Aug. 31, 1998, 525 to 529, from The International Workshop on Field Programable Logic and Applications, FPGAS, Abingon, GB.
1988 IEEE, Patchwork, “Layout From Schematic Annotations,” Richard Barth, Louis Monier and Bertrand Serlet, pp. 250-255.
Kao Russell
Xing Zhaoyun
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Rossoshek H
Smith Matthew
Sun Microsystems Inc.
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